CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications: Design Methodology, Analysis, and Implementation

Cover......Page 1
ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES......Page 3
CMOS Single Chip Fast Frequency
Multi-Gigahertz Applications......Page 4
ISBN-13 9781402059278......Page 5
CONTENTS......Page 6
PREFACE......Page 10
NOMENCLATURE......Page 12
1.1 Introduction......Page 15
1.2 Research Contribution......Page 16
2.1 Introduction......Page 21
2.2 The WLAN Standards......Page 22
2.3 WLAN Transceiver Systems......Page 24
2.3.2 The Receiver......Page 26
2.3.3 The Frequency Synthesizer (Local Oscillator)......Page 27
3.2 Phase-Locked Loop Frequency Synthesizer......Page 29
3.2.1 Phase-Locked Loop Main Blocks......Page 30
3.3 Phase-Locked Loop Parameters......Page 33
3.3.1 Loop Filter Design......Page 34
3.4 Noise in Phase-Locked Loops......Page 41
3.4.1 Component Noise Models......Page 43
3.5 Fractional-N Synthesizers......Page 48
3.5.1 Δ–Σ Modulators in Frequency Synthesizers......Page 50
3.6 RMS Phase Error (φ[sup(rms)]) and Error Vector Magnitude......Page 55
3.7 Conclusion......Page 56
4.1 Introduction......Page 59
4.2 Phase-Domain Model......Page 60
4.2.1 A Constituent Blocks Behavioral Models......Page 64
4.2.2 Noise Modeling Summary......Page 66
4.3 Synthesizer Platform Evaluation......Page 67
4.3.1 Dithering Effect......Page 71
4.3.3 Noise Folding......Page 74
4.3.4 Effect of Prescaler Divider......Page 76
4.4 Conclusion......Page 79
5.2 An overview......Page 81
5.3.1 Design Methodology......Page 83
5.4.1 The Phase-Frequency Detector......Page 85
5.4.2 The Charge Pump......Page 87
5.4.3 3.6 GHz Voltage-Controlled Oscillator......Page 99
5.4.4 The Multimodulus Divider......Page 103
5.4.5 The Fractional Noise Shaping Coder (the Δ–Σ Modulator)......Page 104
5.5 Measured Performance of the Implemented Synthesizer......Page 116
5.6 Summary and Conclusion......Page 121
6.2 Overview......Page 125
6.3.1 PLL Gain and Phase Variations......Page 127
6.3.2 Charge Pump System......Page 130
6.4 Synthesizer Loop Calibration......Page 131
6.5 Process Calibration I/C Slew Rate and RC Time Constant......Page 133
6.6.1 VCO Calibration Algorithm Description......Page 135
6.8 Experimental Results......Page 141
6.10 Conclusion......Page 142
7.1 Conclusion......Page 145
7.2 Further Work......Page 146
1 Phase-Frequency Detectors......Page 149
2 Charge Pump......Page 152
3 PFD/CP Characteristics......Page 154
1.1 Voltage-Controlled Crystal Oscillator......Page 157
1.2 Temperature-Compensated Crystal Oscillator......Page 159
2.1 Voltage-Controlled Oscillators: Phase Noise Analysis......Page 160
2.2 VCO Design Methodology......Page 163
1 Calculation of Global Phase Error From L(f)......Page 171
2 Phase Noise and Phase Modulation......Page 173
3 RMS Phase Error From Phase Noise......Page 175
4 Residual FM......Page 177
1.1 Synchronous Dividers......Page 179
1.2 Asynchronous Reference Frequency Divider......Page 180
2.1 Specification and Different Architecture Evaluation......Page 182
3 High-Speed CMOS Divider Design......Page 191
3.1 Current-Mode Logic Design: An Overview......Page 192
4 Implemented CML Gates......Page 197
1 Mathcad™ Program used for the Simulations of all the Mathcad Figures......Page 201
2 Matlab™ Program used for the Simulations of the Fractional-N PLL Noise Spectrum......Page 212
F......Page 221
W......Page 222