Circuit Design with VHDL

Contents
Chapter 1 - Review of Combinational Circuits
	1.1 - Combinational Circuits
	1.2 - Fundamental Logic Gates
	1.3 - Chain-Type versus Tree-Type Structures
	1.4 - Examples of Combinational Logic Circuits
	1.5 - Examples of Combinational Arithmetic Circuits
	1.6 - Binary Arithmetic
Chapter 2 - Review of Sequential Circuits
	2.1 - Sequential Circuits
	2.2 - Latches
	2.3 - Flip-Flops
	2.4 - Glitch Analysis and Prevention
	2.5 - Register Transfer Level of Abstraction
	2.6 - Initial Examples of Sequential Circuits
	2.7 - Clock Division
	2.8 - Clock Multiplication and Phase-Locked Loops (PLLs)
	2.9 - Asynchronous Data and Synchronizers
	2.10 - Clock Gating
	2.11 - Additional Examples of Sequential Circuits
Chapter 3 - Review of Finite State Machines
	3.1 - Finite State Machines
	3.2 - State Transition Diagram and Machine Types
	3.3 - Representing versus Implementing
	3.4 - Moore-to-Mealy and Mealy-to-Moore Conversion
	3.5 - Time Behavior of Moore versus Mealy Machines
	3.6 - Choosing between Moore and Mealy Machines
	3.7 - Transition Types
	3.8 - Incorrect State Transition Diagrams
	3.9 - Safe State Machines
	3.10 - Fundamental Hardware Architectures for FSMs
	3.11 - Encoding Styles
	3.12 - Fundamental Design Technique for FSMs
	3.13 - State Machine Categories
	3.14 - Dealing with Time
	3.15 - Dealing with Repetitive States
	3.16 - Pointer-Based FSM Implementation
	3.17 - Dealing with Recursivity
	3.18 - Number of Flip-Flops in FSMs
	3.19 - Examples of Category 1 (Regular) State Machines
	3.20 - Examples of Category 2 (Timed) State Machines
	3.21 - Examples of Category 3 (Recursive) State Machines
Chapter 4 - Review of Field Programmable Gate Arrays (FPGAs)
	4.1 - Programmable Logic Devices
	4.2 - PLD Configuration Memories
	4.3 - PAL and PLA Devices
	4.4 - GAL Devices
	4.5 - CPLD Devices
	4.6  - FPGA Devices
Chapter 5 - Introduction to VHDL
	5.1 - About VHDL
	5.2 - Ttransition of VHDL Code into a Circuit
	5.3 - Design Flow
	5.4  - Commercial VHDL Tools
	5.5 - RTL Design Approach
	5.6 - Concurrent versus Sequential Statements
	5.7 - Lexical Elements of VHDL
	5.8 - Choosing Good Names for Your Design
Chapter 6 - Code Structure and Composition
	6.1 - Design Units and Code Structure
	6.2 - Libraries and Packages
	6.3 - Packages List in the Code
	6.4 - Entity Declaration
	6.5 - Architecture Body
	6.6 - Object Classes
	6.7 - Generics
	6.8 - Entity-Architecture Binding
	6.9 - Introductory VHDL Examples
Chapter 7 - Predefined Data Types
	7.1 - Predefined VHDL Types
	7.2 - Type Classes
	7.3 - Type Declarations
	7.4 - Subtypes
	7.5 - A Note on Operators and Attributes
	7.6 - Study of Predefined Data Types
	7.7 - Record Types
	7.8 - Access Types, File Types, and Protected Types
	7.9 - Aggregation, Concatenation, and Resizing
	7.10 - Type Conversion
	7.11 - Type-Qualification Expressions
	7.12 - Additional Examples
	7.13 - Exercises
Chapter 8 - User-Defined Data Types
	8.1 - Review of Synthesizable Predefined Types
	8.2 - User-Defined Types
	8.3 - Building and Addressing Complex Array Types
	8.4 - Checking and Resetting Data Arrays
	8.5 - Classical Mistakes in Assignments
	8.6 - Additional Examples
	8.7 - Exercises
Chapter 9 - Operators and Attributes
	9.1 - Predefined Operators
	9.2 - User-Defined Overloaded Operators
	9.3 - Predefined Attributes
	9.4 - User-Defined Attributes
	9.5 - Synthesis Attributes
	9.6 - Group
	9.7 - Alias
	9.8 - Exercises
Chapter 10 - Concurrent Code
	10.1 - Concurrent Statements
	10.2 - The when Statement
	10.3 - The select Statement
	10.4 - The generate Statement
	10.5 - Component Instantiation Statements
	10.6 - Avoiding Multiple Assignments to the Same Signal
	10.7 - Suggested Approaches for Arithmetic Circuits
	10.8 - Additional Examples and Exercises
Chapter 11 - Concurrent Code: Practice
	11.1 - Additional Design Examples Using Concurrent Code
	11.2 - Exercises
Chapter 12 - Sequential Code
	12.1 - Concurrent Code versus Sequential Code
	12.2 - Detecting Clock Transitions: clk'event or rising_edge(clk)?
	12.3 - The process Statement
	12.4 - The if Statement
	12.5 - The case Statement
	12.6 - The wait Statement
	12.7 - The loop Statement
	12.8 - The Sequential when and select Statements
	12.9 - Signal versus Variable
	12.10 - More about the Updating Rule of Signals and Variables
	12.11 - More about the Inference of Registers Rule
	12.12 - The Problem of Combinational Loops
	12.13 - Additional Examples and Exercises
Chapter 13 - Sequential Code: Practice
	13.1 - Additional Design Examples Using Sequential Code
	13.2 - Exercises
Chapter 14 - Packages and Subprograms
	14.1 - Package
	14.2 - Package with Generics
	14.3 - Function
	14.4 - Procedure
	14.5 - Function versus Procedure Summary
	14.6 - Subprogram with Generics and Generic Subprograms
	14.7 - Overloaded Subprograms
	14.8 - Assert and Report Statements
	14.9 - Exercises
Chapter 15 - The Case of State Machines
	15.1 - The Finite State Machine Approach
	15.2 - State Encoding Styles
	15.3 - VHDL for Regular (Category 1) State Machines
	15.4 - VHDL for Timed (Category 2) State Machines
	15.5 VHDL for Recursive (Category 3) State Machines
	15.6 - Summarizing (and Simplifying) Things
	15.7 - Exercises
Chapter 16 - The Case of State Machines: Practice
	16.1 - Design Examples of Regular (Category 1) State Machines
	16.2 - Design Examples of Timed (Category 2) State Machines
	16.3 - Design Examples of Recursive (Category 3) State Machines
	16.4 - Exercises
Chapter 17 - Additional Design Examples
	17.1 - Additional Design Examples
	17.2 - Exercises
Chapter 18 - Introduction to Simulation with Testbenches
	18.1 - Testbenches
	18.2 - Dealing with Time in VHDL
	18.3 - Stimuli Generation
	18.4 - Complete Testbenches
	18.5 - Practical Considerations on Functional and Timing Simulations
	18.6 - Dealing with Data Files
	18.7 - Running Simulation with Tcl Scripts
	18.8 - Exercises
Appendices
	Appendix A: Vivado Tutorial
	Appendix B: Quartus Prime Tutorial
	Appendix C: ModelSim Tutorial
	Appendix D: Simulation Analysis and Recommendations
	Appendix E: Using Seven-Segment Displays with VHDL
	Appendix F: Serial Peripheral Interface
	Appendix G: I^2C (Inter Integrated Circuits) Interface
	Appendix H: Alphanumeric LCD
	Appendix I: VGA Video Interface
	Appendix J: DVI Video Interface
	Appendix K: TMDS Link
	Appendix L: Using Phase-Locked Loops with VHDL
	Appendix M: List of Enumerated Examples and Exercises
Bibliography
Index