Artificial Intelligence Applications and Reconfigurable Architectures

Cover
Title Page
Copyright Page
Contents
Preface
Chapter 1 Strategic Infrastructural Developments to Reinforce Reconfigurable Computing for Indigenous AI Applications
	1.1 Introduction
	1.2 Infrastructural Requirements for AI
	1.3 Categories in AI Hardware
		1.3.1 Comparing Hardware for Artificial Intelligence
	1.4 Hardware AI Accelerators to Support RC
		1.4.1 Computing Support for AI Application: Reconfigurable Computing to Foster the Adaptation
		1.4.2 Reconfiguration Computing Model
		1.4.3 Reconfigurable Computing Model as an Accelerator
	1.5 Architecture and Accelerator for AI-Based Applications
		1.5.1 Advantages of Reconfigurable Computing Accelerators
		1.5.2 Disadvantages of Reconfigurable Computing Accelerators
	1.6 Conclusion
	References
Chapter 2 Review of Artificial Intelligence Applications and Architectures
	2.1 Introduction
	2.2 Technological Platforms for AI Implementation—Graphics Processing Unit
	2.3 Technological Platforms for AI Implementation—Field Programmable Gate Array (FPGA)
		2.3.1 Xilinx Zynq
		2.3.2 Stratix 10 NX Architecture
	2.4 Design Implementation Aspects
	2.5 Conclusion
	References
Chapter 3 An Organized Literature Review on Various Cubic Root Algorithmic Practices for Developing Efficient VLSI Computing System—Understanding Complexity
	3.1 Introduction
	3.2 Motivation
	3.3 Numerous Cubic Root Methods for Emergent VLSI Computing System—Extraction
	3.4 Performance Study and Discussion
	3.5 Further Research
	3.6 Conclusion
	References
Chapter 4 An Overview of the Hierarchical Temporal Memory Accelerators
	4.1 Introduction
	4.2 An Overview of Hierarchical Temporal Memory
	4.3 HTM on Edge
	4.4 Digital Accelerators
		4.4.1 PIM HTM
		4.4.2 PEN HTM
		4.4.3 Classic
	4.5 Analog and Mixed-Signal Accelerators
		4.5.1 RCN HTM
		4.5.2 RBM HTM
		4.5.3 Pyragrid
	4.6 Discussion
		4.6.1 On-Chip Learning
		4.6.2 Data Movement
		4.6.3 Memory Requirements
		4.6.4 Scalability
		4.6.5 Network Lifespan
		4.6.6 Network Latency
			4.6.6.1 Parallelism
			4.6.6.2 Pipelining
		4.6.7 Power Consumption
	4.7 Open Problems
	4.8 Conclusion
	References
Chapter 5 NLP-Based AI-Powered Sanskrit Voice Bot
	5.1 Introduction
	5.2 Literature Survey
	5.3 Pipeline
		5.3.1 Collect Data
		5.3.2 Clean Data
		5.3.3 Build Database
		5.3.4 Install Required Libraries
		5.3.5 Train and Validate
		5.3.6 Test and Update
		5.3.7 Combine All Models
		5.3.8 Deploy the Bot
	5.4 Methodology
		5.4.1 Data Collection and Storage
			5.4.1.1 Web Scrapping
			5.4.1.2 Read Text from Image
			5.4.1.3 MySQL Connectivity
			5.4.1.4 Cleaning the Data
		5.4.2 Various ML Models
			5.4.2.1 Linear Regression and Logistic Regression
			5.4.2.2 SVM – Support Vector Machine
			5.4.2.3 PCA – Principal Component Analysis
		5.4.3 Data Pre-Processing and NLP Pipeline
	5.5 Results
		5.5.1 Web Scrapping and MySQL Connectivity
		5.5.2 Read Text from Image
		5.5.3 Data Pre-Processing
		5.5.4 Linear Regression
		5.5.5 Linear Regression Using TensorFlow
		5.5.6 Bias and Variance for Linear Regression
		5.5.7 Logistic Regression
		5.5.8 Classification Using TensorFlow
		5.5.9 Support Vector Machines (SVM)
		5.5.10 Principal Component Analysis (PCA)
		5.5.11 Anomaly Detection and Speech Recognition
		5.5.12 Text Recognition
	5.6 Further Discussion on Classification Algorithms
		5.6.1 Using Maximum Likelihood Estimator
		5.6.2 Using Gradient Descent
		5.6.3 Using Naive Bayes’ Decision Theory
	5.7 Conclusion
	Acknowledgment
	References
Chapter 6 Automated Attendance Using Face Recognition
	6.1 Introduction
	6.2 All Modules Details
		6.2.1 Face Detection Model
		6.2.2 Image Preprocessing
		6.2.3 Trainer Model
		6.2.4 Recognizer
	6.3 Algorithm
	6.4 Proposed Architecture of System
		6.4.1 Face Detection Model
		6.4.2 Image Enhancement
		6.4.3 Trainer Model
		6.4.4 Face Recognition Model
	6.5 Conclusion
	References
Chapter 7 A Smart System for Obstacle Detection to Assist Visually Impaired in Navigating Autonomously Using Machine Learning Approach
	7.1 Introduction
	7.2 Related Research
	7.3 Evaluation of Related Research
	7.4 Proposed Smart System for Obstacle Detection to Assist Visually Impaired in Navigating Autonomously Using Machine Learning Approach
		7.4.1 System Description
		7.4.2 Algorithms for Proposed Work
		7.4.3 Devices Required for the Proposed System
	7.5 Conclusion and Future Scope
	References
Chapter 8 Crop Disease Detection Accelerated by GPU
	8.1 Introduction
	8.2 Literature Review
	8.3 Algorithmic Study
	8.4 Proposed System
	8.5 Dataset
	8.6 Existing Techniques
	8.7 Conclusion
	References
Chapter 9 A Relative Study on Object and Lane Detection
	9.1 Introduction
	9.2 Algorithmic Survey
		9.2.1 Object Detection Using Color Masking
			9.2.1.1 Color Masking
			9.2.1.2 Modules/Libraries Used
			9.2.1.3 Algorithm for Color Masking
			9.2.1.4 Advantages and Disadvantages
			9.2.1.5 Verdict
		9.2.2 YOLO v3 Object Detection
			9.2.2.1 YOLO v3
			9.2.2.2 Algorithm Architecture
			9.2.2.3 Advantages and Disadvantages
			9.2.2.4 Verdict
	9.3 YOLO v/s Other Algorithms
		9.3.1 OverFeat
		9.3.2 Region Convolutional Neural Networks
		9.3.3 Very Deep Convolutional Networks for Large-Scale Image Recognition
		9.3.4 Deep Residual Learning for Image Recognition
		9.3.5 Deep Neural Networks for Object Detection
	9.4 YOLO and Its Version History
		9.4.1 YOLO v1
		9.4.2 Fast YOLO
		9.4.3 YOLO v2
		9.4.4 YOLO9000
		9.4.5 YOLO v3
		9.4.6 YOLO v4
		9.4.7 YOLO v5
		9.4.8 PP-YOLO
	9.5 A Survey in Lane Detection Approaches
		9.5.1 Lidar vs. Other Sensors
	9.6 Conclusion
	References
Chapter 10 FPGA-Based Automatic Speech Emotion Recognition Using Deep Learning Algorithm
	10.1 Introduction
	10.2 Related Work
		10.2.1 Machine Learning–Based SER
		10.2.2 Deep Learning–Based SER
	10.3 FPGA Implementation of Proposed SER
	10.4 Implementation and Results
	10.5 Conclusion and Future Scope
	References
Chapter 11 Hardware Implementation of RNN Using FPGA
	11.1 Introduction
		11.1.1 Motivation
		11.1.2 Background
		11.1.3 Literature Survey
		11.1.4 Project Specification
	11.2 Proposed Design
	11.3 Methodology
		11.3.1 Block Diagram Explanation
		11.3.2 Block Diagram for Recurrent Neural Network
		11.3.3 Textual Input Data (One Hot Encoding)
	11.4 PYNQ Architecture and Functions
		11.4.1 Hardware Specifications
	11.5 Result and Discussion
	11.6 Conclusion
	References
Index
EULA