Architecture of Computing Systems: 34th International Conference, ARCS 2021, Virtual Event, June 7–8, 2021, Proceedings

Preface
Organization
Keynote Talks
The Cambrian Explosion in Architecture – Are We “There” Yet?
Brain Inspired Computing
Contents
Memory Organization
Locality: The 3rd Wall and the Need for Innovation in Parallel Architectures
	1 Introduction
	2 Parallel Architectural Archaeology
	3 Evidence of a New Wall - Low Intensity Apps
	4 Further Evidence of a New Wall - Poor Scaling
	5 An Alternative Architecture - Migrating Threads
	6 A Real Example
	7 Conclusions
	References
Static Extraction of Memory Access Profiles for Multi-core Interference Analysis of Real-Time Tasks
	1 Introduction
	2 Related Works
	3 Static Analysis Framework
		3.1 Overview of the Method and Models
		3.2 Extracting a TIPsGraph from a CFG
		3.3 Enumeration of Timed Execution Traces
		3.4 Temporal Segments
	4 Exploitation of the Memory Access Profiles
		4.1 Interference Analysis for Static Scheduling
		4.2 Multi-core WCRT Analysis Techniques
	5 Conclusion and Future Works
	References
Transparent Resilience for Approximate DRAM
	1 Introduction
	2 Background and Related Work
	3 Transparent Resilience for Approximate DRAM
		3.1 Impact of Errors in the Memory Hierarchy
		3.2 Approximate Re-execution
		3.3 Transparent Interface Mechanisms
	4 Methodology
		4.1 Simulation Environment
		4.2 Error and Energy Model
		4.3 Applications and Quality Functions
		4.4 Approximation Levels and Metrics
		4.5 Interfaces for Transparent Resilience
	5 Results
		5.1 Acceptance Tests
		5.2 Approximate Re-execution
		5.3 Transparent Interfaces
	6 Conclusion
	References
Heterogeneous Computing
Automatic Mapping of Parallel Pattern-Based Algorithms on Heterogeneous Architectures
	1 Introduction
	2 Related Work
	3 Parallel Algorithms
		3.1 Parallel Patterns
		3.2 Abstract Pattern Tree
	4 Performance Modeling
	5 Mapping Algorithm
		5.1 Step 1: FlatAPT
		5.2 Step 2: Step Mappings
	6 Evaluation
		6.1 Results
	7 Discussion
	8 Conclusion
	References
Assessing and Improving the Suitability of Model-Based Design for GPU-Accelerated Railway Control Systems
	1 Motivation and Introduction
	2 Background and Related Work
		2.1 Model-Based Design
		2.2 Control Systems
		2.3 GPUs in Critical Systems
	3 Case Study: Design and Implementation of a GPU-Accelerated Parallel Control System
		3.1 Preliminaries
		3.2 The Model
	4 Evaluation
		4.1 Experimental Setup
		4.2 Validation of the Models
		4.3 Integration with External Hardware
		4.4 Evaluation of Generated CUDA Code
		4.5 Improvement of Generated CUDA Code and Its Evaluation
	5 Conclusion and Outlook
	References
DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model
	1 Introduction and Motivation
	2 Background
		2.1 DF-Threads
		2.2 Writing Dataflow Codes with the DF-Threads API
	3 Introducing DRT
		3.1 Debugging with DRT
	4 Evaluation
		4.1 DRT Versus Other Architectural Exploration Tools
	5 Related Work
	6 Conclusion and Future Work
	References
Instruction Set Transformations
Performance Gain of a Data Flow Oriented ISA as Replacement for Java Bytecode
	1 Introduction
	2 Related Work
	3 The Bytecode Based AMIDAR Processor
		3.1 The AMIDAR Principle
		3.2 Java Bytecode as Instruction Set Architecture
		3.3 Data Interconnect
		3.4 Context Switch
		3.5 Garbage Collection
	4 The AMIDAR Processor with New ISA
		4.1 Concept of the ISA
		4.2 Data Interconnect
		4.3 Context Switch
		4.4 Garbage Collection
		4.5 Functional Units
	5 Evaluation
		5.1 Test Setup
		5.2 Scratch Pad Memory
		5.3 Data Interconnect Topology
		5.4 Comparison of ISAs
	6 Conclusion and Future Work
	References
Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA
	1 Introduction
	2 Related Work
	3 System Setup
		3.1 Host Processor
		3.2 CGRA
		3.3 Simulation
	4 Binary Translation
		4.1 Unrolling
		4.2 SCAR-Conversion
		4.3 Memory Disambiguation
		4.4 Scheduling
	5 Evaluation
	6 Conclusion
	References
Organic Computing
An Organic Computing System for Automated Testing
	1 Introduction
	2 Related Work
	3 MLOC in a Nutshell
	4 An Organic Test System
		4.1 Productive Layer
		4.2 Reactive Layer
		4.3 Reflection Layer
		4.4 Collaboration Layer
	5 Evaluation
		5.1 Autonomy
		5.2 Self-organization
		5.3 Robustness
	6 Conclusion and Future Work
	References
Evaluating a Priority-Based Task Distribution Strategy for an Artificial Hormone System
	1 Introduction
	2 Related Work
	3 The Artificial Hormone System
	4 The Priority-Based Task Decision Strategy
		4.1 Overview
		4.2 Time Bounds
	5 Evaluating of the Priority-Based Strategy
		5.1 Evaluation of Self-configuration
		5.2 Evaluation of Self-healing
	6 Improving the Self-healing Time Bound
	7 Conclusion
	References
Low Power Design
Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-core MCUs
	1 Introduction
	2 Related Work
	3 Background
		3.1 PULP Platform
		3.2 Parallel Programming Paradigms
	4 Deriving the SPMD-OMP Model
		4.1 Low-Level Software Support for Parallel Computing
		4.2 Work-Sharing Constructs
		4.3 Event Unit Extensions for Overhead Reduction
		4.4 Mapping OpenMP Directives on the SPMD Paradigm
	5 Benchmarks
	6 Experimental Results
	7 Seizure Detection Application
	8 Conclusion
	References
Energy Efficient Power-Management for Out-of-Order Processors Using Cyclic Power-Gating
	1 Introduction
	2 Cyclic Power-Gating
		2.1 State-Retentive Architecture
	3 Profitability Model for CPG
		3.1 DVFS Interval Models
		3.2 Interval Model for CPG
	4 Simulation Infrastructure and Target Architecture
	5 Results
	6 Related Work
	7 Conclusions
	References
VEFRE Workshop
BCH 2-Bit and 3-Bit Error Correction with Fast Multi-Bit Error Detection
	1 Introduction
	2 BCH Code and Error Correction
	3 BCH Code with Additional Detection
	4 2-Bit Correction with Additional Detection
	5 3-Bit Correction with Additional Detection
	6 General Approach for Errors Higher Than 3-Bit
	References
Evaluating Soft Error Mitigation Trade-offs During Early Design Stages
	1 Introduction
	2 Related Work
		2.1 Methods and Metrics to Model System Reliability
		2.2 Early Stage Resilience Evaluation Frameworks
		2.3 Design for Reliability Cost and Returns
	3 Gem5Panalyzer Implementation
	4 Gem5Panalyzer Evaluation
		4.1 Benchmarks and Experiment Setups
		4.2 Discussion of Results
		4.3 Summary of Toolset Evaluation
	5 PVF Responses to Masking Effects
		5.1 Masking Sweep Methodology and Metrics
		5.2 ROIs of Selected Benchmarks
		5.3 Factors Affect the ROI
		5.4 Optimize the ROI
	6 Summary
	References
Author Index