Architecture of Computing Systems. 36th International Conference, ARCS 2023 Athens, Greece, June 13–15, 2023 Proceedings

Preface
Organization
Keynote Talks
	Reconfigurable Technologies in HPC and Data-Centers. Challenges and Opportunities
	Optimizing the Memory Access Path Across the Computing Stack
	Contents
Accelerating Neural Networks
Energy Efficient LSTM Accelerators for Embedded FPGAs Through Parameterised Architecture Design
	1 Introduction
	2 Related Work
	3 LSTM Background
	4 Solution Design
		4.1 8-Bit Fixed-Point Quantisation
		4.2 Activation Function Optimisation
		4.3 ALU Optimisation
	5 Implementation
		5.1 Activation Function Implementation
		5.2 Pipeline-Based ALU Implementation
		5.3 Parameterised Architecture
	6 Evaluation
		6.1 Experimental Settings
		6.2 Resource Utilisation
		6.3 Throughput
		6.4 Power Consumption and Energy Efficiency
	7 Conclusion and Future Work
	References
A Comparative Study of Neural Network Compilers on ARMv8 Architecture
	1 Introduction
	2 Background
		2.1 The Three Categories of NN Optimizations
		2.2 The NN Compilers Landscape
	3 Basic Features of the Selected Toolchains
	4 Evaluation Methodology
	5 Evaluation Results
	6 Conclusions
	References
Organic Computing Methodology (OC)
A Decision-Theoretic Approach for Prioritizing Maintenance Activities in Organic Computing Systems
	1 Introduction
	2 Related Work
	3 Prerequisites
	4 Methodology
		4.1 Simple Stochastic Planing
		4.2 Complex Stochastic Planing
		4.3 Naive Planing
	5 Evaluation
		5.1 Datacenter Scenario
		5.2 Organic Production Line Scenario
		5.3 Results
		5.4 Discussion
	6 Conclusion and Outlook
	References
Predicting Physical Disturbances in Organic Computing Systems Using Automated Machine Learning
	1 Introduction
	2 Related Work
	3 Prerequisites
	4 Methodology
		4.1 Data Collection and Labeling
		4.2 Bootstrap Phase
		4.3 Optimization Phase
		4.4 Production Phase
	5 Evaluation
		5.1 Implementation and Parametrisation
		5.2 Results
		5.3 Discussion
	6 Conclusion and Outlook
	References
Self-adaptive Diagnosis and Reconfiguration in ADNA-Based Organic Computing
	1 Introduction
	2 Related Work
	3 Diagnosis Architecture
		3.1 Local Diagnosis
		3.2 System Diagnosis
		3.3 Alarms
		3.4 Probes
	4 Adaptive Diagnosis
		4.1 Processing Element Diagnosis
		4.2 Task Diagnosis
		4.3 Probing Based Diagnosis
	5 Quality of Service
	6 Application Reconfiguration
		6.1 Compute Resource Unit
	7 Use Case - Explorer Robot
		7.1 Physical Model
		7.2 Logical Model
		7.3 Initial Configuration
		7.4 Degraded Performance
		7.5 Reconfiguration
		7.6 Results and Evaluation
	8 Conclusion and Future Work
	References
Dependability and Fault Tolerance (VERFE)
Error Codes in and for Network Steganography
	1 Introduction
	2 Background
		2.1 Error Codes
		2.2 Network Steganography
		2.3 Related Work
	3 Combining Error Codes and Steganography
		3.1 Error Correction Codes in Covert Channels
		3.2 Covert Channels in Error Correction Codes
		3.3 Erasure Codes and Covert Channels
	4 Experimental Results
	5 Conclusions
	References
Modified Cross Parity Codes for Adjacent Double Error Correction
	1 Introduction
	2 Related Work
	3 Proposed Method
		3.1 Decoding
		3.2 Checkbit Errors
	4 Burst Detection
	5 Conclusion
	References
Computer Architecture Co-Design
COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores
	1 Introduction
	2 Background and Motivation
	3 Related Work
	4 HPC Architecture
	5 Design Space Exploration Methodology
		5.1 Co-design Exploration: Memory Sub-system
		5.2 Model Validation
	6 Case Studies
		6.1 Unidirectional Approach
	7 Conclusions and Future Work
	References
Post-Silicon Customization Using Deep Neural Networks
	1 Introduction
	2 Intuition
	3 Background and Related Work
	4 Main Idea: Forecaster
		4.1 Phase 1: Building a Predictive Model
		4.2 Phase 2: Prediction-Based Hardware Reconfiguration
	5 Implementation
	6 Experimental Setup
	7 Results
	8 Conclusions
	References
Computer Architectures and Operating Systems
TOSTING: Investigating Total Store Ordering on ARM
	1 Introduction
		1.1 About This Paper
	2 Memory Consistency Models
		2.1 Programming Model
		2.2 Total Store Ordering on x86
		2.3 Weak Ordering on ARM
	3 The Apple M1 Architecture
	4 Evaluation
		4.1 CPU Benchmarks
		4.2 Synthetic Benchmarks
	5 Discussion
	6 Related Work
	7 Conclusion
	References
Back to the Core-Memory Age: Running Operating Systems in NVRAM only
	1 Introduction
	2 Fundamentals and Methodology
		2.1 Hardware Platform
		2.2 Operating Systems
		2.3 Evaluation Approach
	3 Performance Characterisation
	4 Discussion
	5 Related Work
	6 Conclusion
	References
Retrofitting AMD x86 Processors with Active Virtual Machine Introspection Capabilities
	1 Introduction
	2 Background
		2.1 Hardware-Assisted Virtualization
		2.2 Virtual Machine Introspection
	3 State of the Art
		3.1 SLAT-Based Mechanisms
		3.2 Hyper-Single-Stepping
	4 Introspection on the AMD64 Architecture
		4.1 Design
		4.2 Implementation
	5 Evaluation
		5.1 Correctness
		5.2 Stealthiness
		5.3 Performance
	6 Summary
	References
Organic Computing Applications 1 (OC)
Abstract Artificial DNA's Improved Time Bounds
	1 Introduction
	2 Related Work
	3 AHS and ADNA
	4 A2DNA
		4.1 Relation to the ADNA
		4.2 Fundamental Idea
		4.3 Determinability
	5 Determinability Algorithms
		5.1 Naive Algorithm
		5.2 Towards Preprocessing
		5.3 Algorithm with Preprocessing
		5.4 Specification
	6 Conclusion and Future Work
		6.1 Conclusion
		6.2 Future Work
	References
Evaluating the Comprehensive Adaptive Chameleon Middleware for Mixed-Critical Cyber-Physical Networks
	1 Introduction
	2 Related Work
	3 Middleware Architecture and Implementation
		3.1 Middleware Architecture
		3.2 Adaptation
		3.3 Middleware Implementation
	4 Evaluation
		4.1 Evaluation 1: Handling of Dynamic Load Changes
		4.2 Evaluation 2: Handling of Failures
		4.3 Evaluation 3: Effects of Learning
		4.4 Evaluation 4: Exploiting the Potential of CPN
	5 Conclusions
	References
CoLeCTs: Cooperative Learning Classifier Tables for Resource Management in MPSoCs
	1 Introduction
	2 Related Work
	3 Background
		3.1 SOSA
		3.2 Challenges in SOSA
		3.3 Cooperation in LCTs
	4 Design
	5 Evaluation
		5.1 Simulation Setup
		5.2 Results
	6 Conclusion and Outlook
	References
Hardware Acceleration
Improved Condition Handling in CGRAs with Complex Loop Support
	1 Introduction and Motivation
	2 Related Work
	3 Condition Handling in CGRAs
		3.1 CBox
		3.2 CondPE Hardware
		3.3 Scheduler Application Representation - SCAR
		3.4 Scheduler Improvements
	4 Evaluation
		4.1 HW Synthesis
		4.2 Scheduling
		4.3 Combined Evaluation
	5 Conclusion
		5.1 Outlook
	References
FPGA-Based Network-Attached Accelerators – An Environmental Life Cycle Perspective
	1 Introduction
	2 Related Work
		2.1 Communication Model for Network-Attached Accelerators
		2.2 Environmental Life Cycle Assessment for Data Centers
		2.3 Use Cases for Network-Attached Accelerators
	3 Exemplary NAA Framework
	4 Environmental Life Cycle Assessment of NAA Nodes
		4.1 Initial KPI4DCE Observations
		4.2 CPU-Based Nodes
		4.3 NAA-Based Nodes
		4.4 KPI4DCE Evaluation
	5 Conclusion
	References
Optimization of OLAP In-Memory Database Management Systems with Processing-In-Memory Architecture
	1 Introduction
	2 Preliminaries
		2.1 3D-DRAM
		2.2 Processing-In-Memory (PIM)
		2.3 PIM Simulation Environment
	3 Experimental Setup
		3.1 Database Management System
		3.2 Profiler
		3.3 Profiling the Database
		3.4 Simulation Environment
	4 Analysis
		4.1 Finding the Hot Spots
		4.2 Observations and Discussion
		4.3 Analysis of the Bottlenecks
	5 Results
		5.1 PIM Implementation
		5.2 Database Design Considerations with PIM
	6 Conclusion
	References
Organic Computing Applications 2 (OC)
Real-Time Data Transmission Optimization on 5G Remote-Controlled Units Using Deep Reinforcement Learning
	1 Introduction
	2 Related Work
	3 Real-Time Data Transmission Problem
	4 Approach: Deep Reinforcement Learning
		4.1 Background and Model
		4.2 Setup and Hyperparameters
		4.3 Challenges
	5 Evaluation
		5.1 5G Simulation and Scenario
		5.2 Results
	6 Summary
	References
Autonomous Ship Collision Avoidance Trained on Observational Data
	1 Motivation
	2 Background
		2.1 Learning Based Strategies
	3 Approach
		3.1 Automatic Identification System (AIS) as Training Data
		3.2 MASS Collision Avoidance Using PPUU
	4 Evaluation
		4.1 Experimental Setup
		4.2 Results
	5 Discussion
	6 Conclusion
	References
Towards Dependable Unmanned Aerial Vehicle Swarms Using Organic Computing
	1 Introduction
	2 Related Work
	3 Architecture of the ADNA System for Drones
	4 Novel ADNA UAV Elements
		4.1 GroupController
		4.2 PathPlanner
	5 Extension of the ADNA Message Types
		5.1 Prerequisites
		5.2 Implementation
		5.3 Comparison Between Message Types
	6 Evaluation
	7 Conclusion and Future Work
	References
Author Index