Applied Reconfigurable Computing: 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings

Front Matter....Pages I-XVIII
Front Matter....Pages 1-1
Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks....Pages 3-14
A Vector Caching Scheme for Streaming FPGA SpMV Accelerators....Pages 15-26
Hierarchical Dynamic Power-Gating in FPGAs....Pages 27-38
Front Matter....Pages 39-39
Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation....Pages 41-52
ArchHDL: A Novel Hardware RTL Design Environment in C++....Pages 53-64
Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA....Pages 65-76
Front Matter....Pages 77-77
Preemptive Hardware Multitasking in ReconOS....Pages 79-90
A Fully Parallel Particle Filter Architecture for FPGAs....Pages 91-102
TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools....Pages 103-114
Front Matter....Pages 115-115
Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures....Pages 117-128
SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs....Pages 129-140
Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties....Pages 141-152
Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components....Pages 153-164
Front Matter....Pages 165-165
Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays....Pages 167-178
Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip....Pages 179-190
Survey on Real-Time Network-on-Chip Architectures....Pages 191-202
Front Matter....Pages 203-203
Efficient SR-Latch PUF....Pages 205-216
Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study....Pages 217-228
Dual CLEFIA/AES Cipher Core on FPGA....Pages 229-240
Front Matter....Pages 241-241
An Efficient and Flexible FPGA Implementation of a Face Detection System....Pages 243-254
Front Matter....Pages 241-241
A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context....Pages 255-266
A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank....Pages 267-279
The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs....Pages 280-290
Front Matter....Pages 291-291
A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures....Pages 293-300
Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA....Pages 301-310
A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware....Pages 311-320
Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures....Pages 321-330
Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects....Pages 331-338
Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments....Pages 339-348
DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based Systems....Pages 349-356
Acceleration of Data Streaming Classification using Reconfigurable Technology....Pages 357-364
On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach....Pages 365-372
Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform....Pages 373-382
A Challenge of Portable and High-Speed FPGA Accelerator....Pages 383-392
Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array....Pages 393-400
Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture....Pages 401-410
Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization....Pages 411-418
DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost....Pages 419-426
A Flexible Multilayer Perceptron Co-processor for FPGAs....Pages 427-434
Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs....Pages 435-442
Front Matter....Pages 291-291
Towards Performance Modeling of 3D Memory Integrated FPGA Architectures....Pages 443-450
Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL....Pages 451-460
Front Matter....Pages 461-461
Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing....Pages 463-474
SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms....Pages 475-486
Hardware Task Scheduling for Partially Reconfigurable FPGAs....Pages 487-498
SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring....Pages 499-510
Front Matter....Pages 511-511
DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications....Pages 513-518
Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective....Pages 519-530
Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach....Pages 531-541
COSSIM : A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator....Pages 542-553
Back Matter....Pages 555-557