Analysis and Design of Analog Integrated Circuits (4th Edition)

1.2 Depletion Region of a pn junction......Page 16
1.2.1 Depletion-Region Capacitance......Page 20
1.2.2 Junction Breakdown......Page 21
1.3 Large-Signal Behavior of Bipolar Transistors......Page 23
1.3.1 Large-Signal Models in the Forward-Active Region......Page 24
1.3.2 Effects of Collector Voltage on Large-Signal Characteristics in the Forward-Active Region......Page 29
1.3.3 Saturation and Inverse-Active Regions......Page 31
1.3.4 Transistor Breakdown Voltages......Page 35
1.3.5 Dependence of Transistor Current Gain pF on Operating Conditions......Page 38
1.4 Small-Signal Models of Bipolar Transistors......Page 41
1.4.1 Transconductance......Page 42
1.4.2 Base-Charging Capacitance......Page 43
1.4.4 Output Resistance......Page 44
1.4.6 Collector-Base Resistance......Page 45
1.4.7 Parasitic Elements in the Small-Signal Model......Page 46
1.4.8 Specification of Transistor Frequency Response......Page 49
1 5.1 Transfer Characteristics of MOS Devices......Page 53
1.5.2 Comparison of Operating Regions of Bipolar and MOS Transistors......Page 60
1.5.4 Threshold Temperature Dependence......Page 62
1.5.5 MOS Device Voltage Limitations......Page 63
1.6 Small-Signal Models of MOS Transistors......Page 64
1.6.1 Transconductance......Page 65
1.6.2 Intrinsic Gate-Source and Gate-Drain Capacitance......Page 66
1.6.5 Basic Small-Signal Model of the MOS Transistor......Page 67
1.6.6 Body Transconductance......Page 68
1.6.7 Parasitic Elements in the Small-Signal Model......Page 69
1.6.8 MOS Transistor Frequency Response......Page 70
1.7 Short-Channel Effects in MOS Transistors......Page 73
1.7.1 Velocity Saturation from the Horizontal Field......Page 74
1.7.2 Transconductance and Transition Frequency......Page 78
1.8 Weak lnversion in MOS Transistors......Page 80
1.8.1 Drain Current in Weak Inversion......Page 81
1.8.2 Transconductance and Transition Frequency in Weak Inversion......Page 83
1.9 Substrate Current Flow in MOS Transistors......Page 86
A. 1.1 SUMMARY OF ACTIVE-DEVICE PARAMETERS......Page 88
PROBLEMS......Page 90
REFERENCES......Page 91
GENERAL REFERENCES......Page 92
2.2.1 Electrical Resistivity of Silicon......Page 93
2.2.2 Solid-state Diffusion......Page 95
2.2.3 Electrical Properties of Diffused Layers......Page 97
2.2.4 Photolithography......Page 99
2.2.5 Epitaxial Growth......Page 100
2.2.8 Polysilicon Deposition......Page 102
2.3 High-Voltage Bipolar Integrated-Circuit Fabrication......Page 103
2.4 Advanced Bipolar Integrated-Circuit Fabrication......Page 107
2.5 Active Devices in Bipolar Analog lntegrated Circuits......Page 110
2.5.1 Integrated-Circuit npn Transistors......Page 111
2.5.2 Integrated-Circuit pnp Transistors......Page 122
2.6.1 Diffused Resistors......Page 130
2.6.2 Epitaxial and Epitaxial Pinch Resistors......Page 134
2.6.3 Integrated-Circuit Capacitors......Page 135
2.6.4 Zener Diodes......Page 136
2.6.5 Junction Diodes......Page 137
2.7.1 Dielectric Isolation......Page 138
2.7.2 Compatible Processing for High-Performance Active Devices......Page 139
2.8 MOS Integrated-Circuit Fabrication......Page 142
2.9.1 n-Channel Transistors......Page 146
2.9.2 p-Channel Transistors......Page 156
2.9.4 Bipolar Transistors......Page 157
2.10.1 Resistors......Page 159
2.10.2 Capacitors in MOS Technology......Page 160
2.10.3 Latchup in CMOS Technology......Page 163
2.11 BiCMOS Technology......Page 165
2.12 Heterojunction Bipolar Transistors......Page 167
2.13 Interconnect Delay......Page 168
2.14.1 Yield Considerations in Integrated-Circuit Fabrication......Page 169
2.14.2 Cost Considerations in Integrated-Circuit Fabrication......Page 172
2.15.1 Maximum Power Dissipation......Page 174
2.15.2 Reliability Considerations in Integrated-Circuit Packaging......Page 177
A.2.1 SPICE MODEL-PARAMETER FILES......Page 178
PROBLEMS......Page 179
REFERENCES......Page 182
3. Single-Transistor and Multiple-Transistor Amplifiers......Page 185
3.1 Device Model Selection for Approximate Analysis of Analog Circuits......Page 186
3.2 Two-Port Modeling of Amplifiers......Page 187
3.3 Basic Single-Transistor Amplifier Stages......Page 189
3.3.1 Common-Emitter Configuration......Page 190
3.3.2 Common-Source Configuration......Page 194
3.3.3 Common-Base Configuration......Page 198
3.3.4 Common-Gate Configuration......Page 201
3.3.5.1 Common-Base and Common-Gate lnput Resistance......Page 203
3.3.5.2 Common-Base and Common-Gate Output Resistance......Page 205
3.3.6 Common-Collector Configuration (Emitter Follower)......Page 206
3.3.7 Common-Drain Configuration (Source Follower)......Page 210
3.3.8 Common-Emitter Amplifier with Emitter Degeneration......Page 212
3.3.9 Common-Source Amplifier with Source Degeneration......Page 215
3.4.1 The CC-CE, CC-CC and Darlington Configurations......Page 217
3.4.2.1 The Bipolar Cascode......Page 221
3.4.2.2 The MOS Cascode......Page 223
3.4.3 The Active Cascode......Page 226
3.4.4 The Super Source Follower......Page 228
3.5.1 The dc Transfer Characteristic of an Emitter-Coupled Pair......Page 230
3.5.2 The dc Transfer Characteristic with Emitter Degeneration......Page 232
3.5.3 The dc Transfer Characteristic of a Source-Coupled Pair......Page 233
3.5.4 Introduction to the Small-Signal Analysis of Differential Amplifiers......Page 236
3.5.5 Small-Signal Characteristics of Balanced Differential Amplifiers......Page 239
3.5.6.1 Input Offset Voltage and Current......Page 246
3.5.6.2 Input Offset Voltage of the Emitter-Coupled Pair......Page 247
3.5.6.4 Offset Voltage Drift in the Emitler-Coupled Pair......Page 249
3.5.6.5 Input Offset Current of the Emitter-Coupled Pair......Page 250
3.5.6.6 Input Offset Voltage of the Source-Coupled Pair......Page 251
3.5.6.9 Small-Signal Characteristics of Unbalanced Differential Amplifiers......Page 253
A.3.1 ELEMENTARY STATISTICS AND THE GAUSSIAN DlSTRl BUTION......Page 261
PROBLEMS......Page 263
BIBLIOGRAPHY......Page 267
4.2.1 General Properties......Page 268
4.2.2.1 Bipolar......Page 270
4.2.2.2 MOS......Page 272
4.2.3.1 Bipolar......Page 275
4.2.4.1 Bipolar......Page 277
4.2.5.1 Bipolar......Page 278
4.2.5.2 MOS......Page 281
4.2.6.1 Bipolar......Page 289
4.2.6.2 MOS......Page 292
4.3.1 Motivation......Page 293
4.3.2 Common-Emitter/Common-Source Amplifier with Complementary Load......Page 294
4.3.3 Common-Emitter/Common-Source Amplifier with Depletion Load......Page 297
4.3.4 Common-Emitter/Common-Source Amplifier with Diode-Connected Load......Page 299
4.3.5.1 Large-Signal Analysis......Page 302
4.3.5.2 Small-Signal Analysis......Page 303
4.3.5.3 Common-Mode Rejection Ratio......Page 308
4.4.1.1 Bipolar Widlar Current Source......Page 314
4.4.1.2 MOS Widlar Current Source......Page 317
4.4.1.3 Bipolar Peaking Current Source......Page 318
4.4.1.4 MOS Peaking Current Source......Page 319
4.4.2.1 Widlar Current Sources......Page 321
4.4.2.2 Current Sources Using Other Voltage Standards......Page 322
4.4.2.3 Self Biasing......Page 324
4.4.3.1 Band-Gap-Referenced Bias Circuits in Bipolar Technology......Page 332
4.4.3.2 Band-Gap-Referenced Bias Circuits in CMOS Technology......Page 338
A.4.1.1 BIPOLAR......Page 342
A.4.1.2 MOS......Page 344
A.4.2.1 BIPOLAR......Page 347
A.4.2.2 MOS......Page 349
PROBLEMS......Page 351
REFERENCES......Page 358
5.2.1 Transfer Characteristics of the Emitter-Follower......Page 359
5.2.2 Power Output and Efficiency......Page 362
5.2.3 Emitter-Follower Drive Requirements......Page 369
5.2.4 Small-Signal Properties of the Emitter Follower......Page 370
5.3.1 Transfer Characteristics of the Source Follower......Page 371
5.3.2 Distortion in the Source Follower......Page 373
5.4 Class B Push-Pull Output Stage......Page 377
5.4.1 Transfer Characteristic of the Class B Stage......Page 378
5.4.2 Power Output and Efficiency of the Class B Stage......Page 380
5.4.3 Practical Realizations of Class B Complementary Output Stages6......Page 384
5.4.4 All-npn Class B Output Stage......Page 391
5.4.5 Quasi-Complementary Output Stages......Page 394
5.4.6 Overload Protection......Page 395
5.5 CMOS Class AB Output Stages......Page 397
5.5.1 Common-Drain Configuration......Page 398
5.5.2 Common-Source Configuration with Error Amplifiers......Page 399
5.5.3.1 Combined Common-Drain Common-Source Configuration......Page 406
5.5.3.2 Combined Common-Drain Common-Source Configuration with High Swing......Page 408
5.5.3.3 Parallel Common-Source Configuration......Page 409
PROBLEMS......Page 413
REFERENCES......Page 418
6. Operational Amplifiers with Single-Ended Outputs......Page 419
6.1.1 Basic Feedback Concepts......Page 420
6.1.2 Inverting Amplifier......Page 421
6.1.4 Differential Amplifier......Page 423
6.1.5 Nonlinear Analog Operations......Page 424
6.1.6 Integrator, Differentiator......Page 425
6.1.7.1 Switched-Capacitor Amplifier......Page 426
6.1.7.2 Switched-Capacitor Integrator......Page 431
6.2.1 Input from Current......Page 434
6.2.3 Input Offset Voltage......Page 435
6.2.5 Common-Mode Rejection Ration (CMRR)......Page 436
6.2.6 Power-Supply Rejection Ratio (PSRR)......Page 437
6.2.10 Operational-Amplifier Equivalent Circuit......Page 439
6.3 Basic Two-Stage MOS Operational Amplifiers......Page 440
6.3.1 Input Resistance, Output Resistance, and Open-Circuit Voltage Gain......Page 441
6.3.3 Input Offset Voltage......Page 443
6.3.4 Common-Mode Rejection Ratio......Page 446
6.3.5 Common-Mode Input Range......Page 447
6.3.6 Power-Supply Rejection Ratio (PSRR)......Page 449
6.3.8 Layout Considerations......Page 454
6.4 Two-Stage MOS Operational Amplifiers with Cascodes......Page 457
6.5 MOS Telescopic-Cascode Operational Amplifiers......Page 459
6.6 MOS Folded-Cascode Operational Amplifiers......Page 461
6.7 MOS Active-Cascode Operational Amplifiers......Page 465
6.8 Bipolar Operational Amplifiers......Page 468
6.8.1 The dc Analysis of the 741 Operational Amplifier......Page 472
6.8.2 Small-Signal Analysis of the 741 Operational Amplifiers......Page 477
6.9 Design Consideretions for Bipolar Monolithic Operational Amplifiers......Page 487
6.9.1 Design of Low-Drift Operational Amplifiers......Page 489
6.9.2 Design of Low-Input-Current Operational Amplifiers......Page 491
Problems......Page 495
References......Page 502
7.2.1 Single-Stage Voltage Amplifiers and the Miller Effect......Page 503
7.2.1.1 The Bipolar Differential Amplifier, Differential-Mode Gain......Page 508
7.2.1.2 The MOS Differential Amplifier. Differential Mode Gain......Page 511
7.2.2 Frecuancy Response of the Common-Mode Gain for a Differential Amplifier......Page 514
7.2.3 Frecuency Response of Voltage Buffers......Page 517
7.2.3.1 Frecuency Response of the Emitter Follower......Page 518
7.2.3.2 Frecuency Response of the Source Follower......Page 524
7.2.4 Frecuency Response of Current Buffers......Page 527
7.2.4.1 Common-Base Amplifier Frecuency Response......Page 529
7.2.4.2 Common-Gate Amplifier Frecuency Response......Page 530
7.3.1 Dominant-Pole Approximation......Page 531
7.3.2 Zero-Value Time Constant Analysis......Page 532
7.3.3 Cascade Voltage-Amplifier Frecuency Response......Page 537
7.3.4 Cascode Frecuency Response......Page 540
7.3.5 Frecuency Response of a Current Mirror Loading a Differential Pair......Page 547
7.3.6 Short-Circuit Time Constants......Page 548
7.4.1 Hign-Frecuency Equivalent Circuit of the 741......Page 552
7.4.2 Calculation of the -3-db Frecuency of the 741......Page 553
7.4.3 Nondominat Poles of the 741......Page 555
7.5 Relation Between Frecuency Response and Time Response......Page 557
Problems......Page 559
References......Page 567
8.1 Ideal Feedback Equation......Page 568
8.3 Effect of Negative Feedback on Distorsion......Page 570
8.4.1 Series-Shunt Feedback......Page 572
8.4.2 Shunt-Shunt Feedback......Page 575
8.4.3 Shunt-Series Feedback......Page 576
8.4.4 Series-Series Feedback......Page 577
8.5.1 Shunt-Shunt Feedback......Page 578
8.5.2 Series-Series Feedback......Page 584
8.5.3 Series-Shunt Feedback......Page 594
8.5.4 Shunt-Series Feedback......Page 598
8.6.1 Local Series-Series Feedback......Page 602
8.6.2 Local Series-Shunt Feedback......Page 606
8.7 The Voltage Regulator as a Feedback Circuit......Page 608
8.8 Feedback Circuit Analysis Using Return Ratio......Page 614
8.8.1 Closed-Loop Gain Using Return Ratio......Page 616
8.8.2 Closed-Loop Impedance Formula Using Return Ratio......Page 622
8.8.3 Summary-Return-Ratio Analysis......Page 627
8.9 Modelling Input and Output Ports in Feedback Circuits......Page 628
Problems......Page 630
References......Page 638
9. Frequency Response and Stability of Feedback Amplifiers......Page 4
9.2 Relation Between Gain and Bandwidth in Feedback Amplifiers......Page 639
9.3 Instability and the Nyquist Criterion......Page 641
9.4.1 Theory of Compensation......Page 648
9.4.2 Methods of Compensation......Page 652
9.4.3 Two-Stage MOS Amplifier Compensation......Page 659
9.4.4 Compensation of Single-Stage CMOS Op Amps......Page 667
9.4.5 Nested Miller Compensation......Page 671
9.5.1 Root Locus for Three-Pole Transfer Function......Page 679
9.5.2 Rules for Root-Locus Construction......Page 682
9.5.3 Root Locus for Dominant-Pole Compensation......Page 690
9.5.4 Root Locus for Feedback-Zero Compensation......Page 691
9.6.1 Origin of Slew-Rate Limitations......Page 695
9.6.2 Methods of Improving Slew-Rate in Two-Stage Op Amps......Page 699
9.6.3 Improving Slew-Rate in Bipolar Op AMps......Page 700
9.6.4 Improving Slew Rate in MOS Op Amps......Page 701
9.6.5 Effect of Slew-Rate Limitations on Large-Signal Sinusoidal Performance......Page 705
A9.1 Ananysis in terms of Return-Ratio Parameters......Page 706
A9.2 Roots of a quadratic Equation......Page 707
Problems......Page 710
References......Page 715
10.2 Precision Rectification......Page 717
10.3.1 The Emitter-Coupled Pair as a Dimple Multiplier......Page 723
10.3.2 The dc Analysis of the Gilbert Multiplier Cell......Page 725
10.3.3 The Gilbert Cell as an Analog Multiplier......Page 727
10.3.4 A Complete Analog Multiplier......Page 730
10.3.5 The Gilbert Cell as a Balanced Modulator and Phase Detector......Page 731
10.4.1 Phase-Locked Loop Concepts......Page 735
10.4.2 The Phase-Locked Loop in the Locked Condition......Page 737
10.4.3 Integrated-Circuit Phase-Locked Loops......Page 746
10.4.4 Analysis of the 560B Monolithic Phase-Locked Loop......Page 750
10.5 Nonlinear Function Synthesis......Page 758
Problems......Page 759
References......Page 762
11.2.1 Shot Noise......Page 763
11.2.2 Thermal Noise......Page 767
11.2.3 Flicker Noise (1/f Noise)......Page 768
11.2.4 Burst Noise (Popcorn Noise)......Page 769
11.2.5 Avalanche Noise......Page 770
11.3.1 Junction Diode......Page 771
11.3.2 Bipolar Transistor......Page 772
11.3.3 MOS Transistor......Page 773
11.3.5 Capacitors and Inductors......Page 774
11.4 Circuit Noise Calculations......Page 775
11.4.1 Bipolar Transistor Noise Performance......Page 777
11.4.2 Equivalent Input Noise and the Minimun Detectable Signal......Page 781
11.5.1 Bipolar Transistor Noise Generators......Page 783
11.5.2 MOS Transistor Noise Generators......Page 788
11.6.1 Effect of Ideal Feedback on Noise Performance......Page 791
11.6.2 Effect of Practical Feedback on Noise Performance......Page 792
11.7.1 Coomon-Base Stage Noise Performance......Page 798
11.7.2 Emitter-Follower Noise Performance......Page 799
11.7.3 Differential-Pair Noise Performance......Page 800
11.8 Noise in Operational Amplifiers......Page 803
11.9 Noise Bandwidth......Page 809
11.10.1 Noise Figure......Page 814
11.10.2 Noise Temperature......Page 817
Problems......Page 818
References......Page 822
12.2 Properties of Fully Differential Amplifiers......Page 823
12.3 Small-Signal Models for Balanced Differential Amplifiers......Page 826
12.4 Common-Mode Feedback......Page 831
12.4.1 Common-Mode Feedback of Low Frequencies......Page 832
12.4.2 Stability and Compensation Considerations in a CMFB Loop......Page 837
12.5 CMFB Circuits......Page 838
12.5.1 CMFB Using Resistive Divider and Amplifier......Page 839
12.5.2 CMFB Using Two Differential Pairs......Page 843
12.5.3 CMFB Using Transistors in the Triode Region......Page 845
12.5.4 Switched-Capacitor CMFB......Page 847
12.6.1 A fully Differential Two-Stage Op Amp......Page 850
12.6.2 Fully Differential Telescopic Cascode Op Amp......Page 860
12.6.3 Fully Differential Folded-Cascode Op Amp......Page 861
12.6.4 A differential Op Amp with Two Differential Input Stages......Page 862
12.6.5 Neutralization......Page 864
12.7 Unbalanced Fully Differential Circuits......Page 865
12.8 Bandwidth of the CMFB Loop......Page 871
Problems......Page 872
References......Page 878
Index......Page 879