AI-Enabled Electronic Circuit and System Design : From Ideation to Utilization

Preface
Special thanks to following chapter reviewers:
Contents
1 AI-Assisted Circuit Design and Modeling
	1.1 Introduction
	1.2 Traditional IC Design, Modeling, and Their Challenges
	1.3 Brief on Artificial Intelligence and Machine Learning Techniques
		1.3.1 Supervised Learning
		1.3.2 Unsupervised Learning
		1.3.3 Reinforcement Learning
	1.4 AI-Assisted Device Design and Modeling
		1.4.1 Device Characterization and Modeling
			1.4.1.1 Methodology
			1.4.1.2 Training Data Generation
			1.4.1.3 State-of-the-Art Works
		1.4.2 Device Sizing
			1.4.2.1 Problem Statement
			1.4.2.2 State-of-the-Art Works
	1.5 AI-Assisted Circuit Design and Modeling
		1.5.1 Methodology
		1.5.2 State-of-the-Art Works
		1.5.3 Reliability Verification
	1.6 Challenges and Opportunities
	1.7 Conclusion
	1.8 Future Trends
	References
2 Linking System and Circuit Design by AI Techniques
	2.1 Introduction
		2.1.1 SysMLv2 and SysMD
			2.1.1.1 SysMLv2
			2.1.1.2 SysMD: Bridging the Gap in Systems Modeling
	2.2 Design Capture with SysMLv2
		2.2.1 Abstraction Layers in the AMS Design
		2.2.2 Example Tire Pressure Meter System (TPMS)
		2.2.3 System Modeling and SysMLv2
		2.2.4 Refinement of Requirement Model
		2.2.5 Summary and Conclusion
	2.3 Digital Twin as a Connector Between the Engineer and the System Model
		2.3.1 Description SysMD Model
		2.3.2 Further Processing of the Data
		2.3.3 Summary and Conclusion
	2.4 Knowledge Base
		2.4.1 Motivation
		2.4.2 How to Design Well-Founded Knowledge Bases
			2.4.2.1 Ontology Design Process
			2.4.2.2 Top-Level Ontologies
		2.4.3 An Ontology for Electronic Design: The GENIAL! Basic Ontology (GBO)
			2.4.3.1 Overview
			2.4.3.2 Reasoning and Axiomatization
		2.4.4 Electronic Knowledge Base of Systems, Hardware, and Software
		2.4.5 Summary and Conclusion
	2.5 Knowledge Base Construction with Natural Language Processing
		2.5.1 Introduction
		2.5.2 Background
		2.5.3 Motivation and Approach
			2.5.3.1 Dataset
			2.5.3.2 Bi-LSTM
			2.5.3.3 Relationship Establishment
		2.5.4 Results
		2.5.5 Conclusion
	2.6 SysMD Code Generation with Transformer Neural Network
		2.6.1 Introduction
		2.6.2 Background
		2.6.3 Methodology
		2.6.4 Results and Evaluation
		2.6.5 Conclusion
	2.7 Automotive Electrical System (Boardnet) Application
		2.7.1 Introduction to Automotive Boardnet Design
			2.7.1.1 Evolution of Boardnet Architecture
			2.7.1.2 Requirements and Challenges
		2.7.2 Automotive Electrical System Architectures
			2.7.2.1 Traditional Boardnet Architectures
			2.7.2.2 Disruptive Paradigm Shift
			2.7.2.3 Intelligent Zonal and Centralized Boardnet Concepts
		2.7.3 AI-Enabled Semantic Modeling for Enhanced Integration
			2.7.3.1 Advantages of AI-Driven Boardnet Design
			2.7.3.2 Future Prospects and Challenges
			2.7.3.3 Semantic Model of the Boardnet and Reasoning Application
		2.7.4 Preliminary Conclusions
	2.8 Conclusion
	References
3 AI-Enabled Efficient Memory Design for Data-Intensive Applications
	3.1 Introduction
	3.2 Background
		3.2.1 Memory in Video Streaming
		3.2.2 Memory in Deep Learning
		3.2.3 Emerging Memory Technologies
	3.3 State of the Art
		3.3.1 Low-Power CMOS Memory Design
			3.3.1.1 CMOS General-Purpose Memory Design
			3.3.1.2 Application-Specific Memory Design
		3.3.2 Low-Power Emerging Memory Design
	3.4 AI-Enabled Low-Power Memory Design Methodology
		3.4.1 AI-Enabled Content-Adaptive Video Memory
		3.4.2 ROI-Aware Low-Power Bit Truncation Memory Design
		3.4.3 AI-enabled Low-Cost Self-Recovery Memory for Videos and Deep Learning
	3.5 Open Research Problems and Potential Solutions
		3.5.1 AI-Based Data Study Perspective
		3.5.2 Hardware Design Perspective
		3.5.3 Application Perspective
	3.6 Conclusion
	References
4 AI-Enabled Static Timing Analysis at Early Stages of the Digital Design Flow
	4.1 Introduction
	4.2 Static Timing Analysis
	4.3 Related Work
		4.3.1 Non-ML-Based Approaches
			4.3.1.1 Analytical
			4.3.1.2 Macro-Modeling
			4.3.1.3 Polynomial
		4.3.2 ML-Based Approaches
			4.3.2.1 Shallow Methods and Deep Neural Networks
			4.3.2.2 Graph Neural Networks
		4.3.3 Summary
	4.4 Training Data Collection Flow
		4.4.1 An Automated Specification-to-RTL Flow
			4.4.1.1 MetaRTL Structure
			4.4.1.2 Generating Training Circuits
		4.4.2 RTL-to-Gate-Level Flow
			4.4.2.1 Logic Synthesis
			4.4.2.2 Timing Analysis
	4.5 Pin-to-Pin Component Delay and Slew Estimation
		4.5.1 Problem Statement
		4.5.2 Dataset Collection and Feature Selection
			4.5.2.1 Tabular Datasets
			4.5.2.2 Graph Dataset (DS-III)
		4.5.3 Machine Learning Models
			4.5.3.1 MLP-Based Models
			4.5.3.2 GNN-Based Models
		4.5.4 Evaluation Circuits
		4.5.5 Experimental Results
			4.5.5.1 Inference Using MLPs and Dataset I
			4.5.5.2 Inference Using MLPs and Dataset II
			4.5.5.3 Inference Using GNNs and Dataset III
		4.5.6 Summary
	4.6 AI-Enabled Static Timing Analysis
		4.6.1 Problem Statement
		4.6.2 Consolidation of Pin-to-Pin Delay Models
			4.6.2.1 Selection of Training Circuits
			4.6.2.2 Varying Timing Constraints for Training Data
			4.6.2.3 One Model per Component Type
		4.6.3 Static Timing Analysis Flow
			4.6.3.1 Graph Traversal
			4.6.3.2 Forward Pass: AT Propagation
			4.6.3.3 Backward Pass: RAT Propagation and Slack Calculation
		4.6.4 Experimental Results
		4.6.5 Summary
	4.7 Potential Application
		4.7.1 Micro-Architectural Transformations
			4.7.1.1 Multiplexer Trees
		4.7.2 Micro-Architecture Search
	4.8 Summary and Conclusions
	References
5 Harnessing Graph Learning for Efficient Timing Signoff
	5.1 Introduction
	5.2 Graph Learning-Based Model for Fast and Accurate Interconnect Delay Prediction at Single Corner
		5.2.1 Interconnects in Advanced Process Nodes
		5.2.2 Transformation of RC Networks into Graph Representation
		5.2.3 Customized GNN Model for Interconnect Delay Prediction
		5.2.4 Augmentation with Additional Feature
		5.2.5 Evaluation Results
			5.2.5.1 Experimental Setup
			5.2.5.2 Accuracy Comparison
			5.2.5.3 Error Analysis
			5.2.5.4 Runtime Comparison
		5.2.6 Summary
	5.3 Cross-Corner Signoff Timing Prediction with Learning-Based Approaches
		5.3.1 Prior Cross-Corner Signoff Timing Prediction Approaches
		5.3.2 Overview of Learning-Based Cross-Corner Signoff Timing Framework
		5.3.3 Learning-Based Known RC Corner Selection
		5.3.4 Graph Learning-Based Cross-Corner Interconnect Timing Prediction
		5.3.5 Integration with ECO Flow
		5.3.6 Evaluation Results
			5.3.6.1 Experimental Setup
			5.3.6.2 Interconnect Delay Prediction Accuracy in Sub-10nm
			5.3.6.3 Interconnect Delay Prediction Accuracy in 28nm
			5.3.6.4 Cross-Corner Interconnect Slew and Load Prediction
			5.3.6.5 ECO Runtime Improvement
			5.3.6.6 Known Corner Selection Accuracy
		5.3.7 Summary
	5.4 Conclusions and Outlook
	References
6 AI-Enabled Placement for 2D and 3D ICs
	6.1 Introduction
		6.1.1 Overview of 2D Placement Problem in VLSI Design
		6.1.2 Role of AI in Placement Algorithms
		6.1.3 Motivation for AI-Enabled Placement
	6.2 Fundamentals of AI Techniques for Placement
		6.2.1 Overview of Machine Learning Algorithms
		6.2.2 Supervised, Unsupervised, and Reinforcement Learning
		6.2.3 Machine Learning Algorithms
		6.2.4 Deep Learning and Convolutional Neural Networks
	6.3 Essentials of Reinforcement Learning (RL)-Based Placement Algorithms
		6.3.1 RL Algorithms for VLSI Placement and Their Classification
		6.3.2 Placement Representations as the Input of RL Policy
		6.3.3 Action as the Output of the RL Policy
		6.3.4 RL Policy for Placement Algorithms
	6.4 AI-Enabled 2D Placement Algorithms
		6.4.1 AI-Based Algorithm Using GPU Acceleration
		6.4.2 AI-Enabled Algorithm for Placement of Macros (Floorplanning)
		6.4.3 AI-Enabled Algorithm for Initial Solution
		6.4.4 AI-Enabled Algorithm for Parameters Tuning
		6.4.5 AI-Enabled Algorithm with PPA Co-optimization
		6.4.6 AI-Enabled Algorithm with Routing Cooperation
		6.4.7 Comparison of AI-Enabled 2D Placement Techniques
	6.5 AI-Enabled 3D Placement Algorithms
		6.5.1 3D Integration Technologies
		6.5.2 3D Placement Problem
		6.5.3 3D Placement Strategies
		6.5.4 Review of 3D Placement Algorithms
		6.5.5 AI-Enabled 3D Placement for Initial Solution
		6.5.6 AI-Enabled 3D Placement Using Parameters Tuning
		6.5.7 3D Placement with PPA Co-optimization
		6.5.8 Comparison of AI-Enabled 3D Placement Techniques
	6.6 How to Design and Characterize RL Components?
		6.6.1 Problem Formulation
		6.6.2 RL Design and Characterization Framework (RLDCF)
		6.6.3 RS3DPlace RL Design Case-Study
		6.6.4 RS3DPlace Policy Model Selection
		6.6.5 Characterization of RS3DPlace Placement Representation
		6.6.6 Characterization of RS3DPlace Action Representation
		6.6.7 Application to 2D Placement Problem
	6.7 Research Challenges
	6.8 Summary
	References
7 Enhancing FPGA CAD Flow with AI-Powered Solutions
	7.1 What Is FPGA?
	7.2 Overview of the FPGA CAD Flow
	7.3 AI-Powered HDL Generation
		7.3.1 Conventional High-Level Synthesis
		7.3.2 ML-Based Metric Prediction Algorithms in HLS
		7.3.3 ML-Based Design Space Exploration in HLS
	7.4 AI-Powered Logic Synthesis
		7.4.1 Procedure of FPGA Synthesis
		7.4.2 Reinforcement Learning-Based Logic Optimization and Technology Mapping
		7.4.3 Fast and Accurate Synthesis Result Estimation with ML
		7.4.4 ML-Powered Time Convergence in FPGA Synthesis
	7.5 AI-Powered Placement
		7.5.1 Conventional Placement Algorithms
		7.5.2 ML-Based Congestion Estimation
		7.5.3 ML-Based Routability Prediction
	7.6 AI-Powered Routing
		7.6.1 ML-Based Routability Prediction
	References
8 AI-Enabled 3D Integration
	8.1 Introduction to 3D Integration
		8.1.1 Advantage of 3D Integration Compared to 2D/2.5D IC Packaging Technology
		8.1.2 Types and Architectures of 3D Integration
		8.1.3 Challenges and Opportunity in 3D Integration
		8.1.4 Possibility of AI Application in 3D Integration
	8.2 Artificial Intelligence in 3D Integration
		8.2.1 Introduction to Artificial Intelligence
		8.2.2 AI Techniques and Algorithms for 3D Integration
		8.2.3 Application of AI in 3D Integration
	8.3 AI-Enabled Testing and Quality Assurance in 3D Integration
		8.3.1 AI-Based Testing Approaches and Strategies
		8.3.2 Quality Assurance Technique in 3D Integration
		8.3.3 Case Studies
	8.4 AI-Enhanced Reliability and Failure Analysis in 3D Integration
		8.4.1 Reliability Challenges in 3D Integration
		8.4.2 AI-Based Reliability Prediction and Analysis
	8.5 AI-Driven Manufacturing and Assembly in 3D Integration
		8.5.1 AI-Based Manufacturing Process in 3D Integration
		8.5.2 Assembly Techniques and Optimization with AI
		8.5.3 Robotics and Automation in 3D Integration
	8.6 Future Directions and Emerging Trends
		8.6.1 Promising Trends and Technologies
		8.6.2 Research Challenges and Opportunities
		8.6.3 Ethical Challenges and Implications
		8.6.4 Privacy and Security Concerns
		8.6.5 AI-Driven 3D Integration in Industry
	8.7 Summary
	References
9 AI-Enabled Hardware Security
	9.1 Introduction
	9.2 AI-Enabled Side-Channel Analysis
		9.2.1 Workflow
		9.2.2 Sketching the Classic Approach
			9.2.2.1 CMOS Technology
			9.2.2.2 Example Implementation
			9.2.2.3 Leakage Model
			9.2.2.4 Feature Engineering and Countermeasures
			9.2.2.5 Leakage Exploitation
		9.2.3 Machine-Learning-Based Approaches
			9.2.3.1 Leakage Detection and Leakage Assessment
			9.2.3.2 Leakage Exploitation Using ML
		9.2.4 Summary
	9.3 Hardware Reverse Engineering
		9.3.1 Digital Circuits Reverse Engineering
		9.3.2 Hardware Trojan Detection
		9.3.3 Recycled FPGA Detection
		9.3.4 Outlook and Discussion
	9.4 AI-Enabled Analysis of Physical Unclonable Functions
		9.4.1 Physical Unclonable Functions
		9.4.2 Attacks
		9.4.3 Attack-Resistant Lockdown Protocols
			9.4.3.1 Definition and Notation
			9.4.3.2 Lockdown Protocol I
			9.4.3.3 Lockdown Protocol II
		9.4.4 Outlook and Discussion
	9.5 Conclusion
	References
10 On AI-Enabled Cybersecurity: Zero-Day Malware Detection
	10.1 Security Vulnerabilities
	10.2 Malware Attacks
		10.2.1 Get Familiar with Malware Types
			10.2.1.1 Virus
			10.2.1.2 Worm
			10.2.1.3 Trojans
			10.2.1.4 Spyware
			10.2.1.5 Adware
			10.2.1.6 Ransomware
			10.2.1.7 Rootkit
			10.2.1.8 Botnet
			10.2.1.9 Backdoor
		10.2.2 Unknown (Zero-Day) Malware Attacks
	10.3 Malware Detection Techniques
		10.3.1 Signature-Based Malware Detection
		10.3.2 Behavior-Based Malware Detection
	10.4 Machine Learning Algorithms
		10.4.1 Classical Machine Learning
		10.4.2 Deep Learning
			10.4.2.1 Multilayer Perceptron
			10.4.2.2 Convolutional Neural Network
			10.4.2.3 Recurrent Neural Network
			10.4.2.4 Large Language Models and Transformers
	10.5 Machine Learning-Enabled Malware Detection
		10.5.1 Process of ML-Enabled Malware Detection Approach
		10.5.2 ML-Based Malware Detection in Windows Systems Using Strings Extracted from PE Files
		10.5.3 Android Malware Detection Using Machine Learning and a Hybrid Feature Analysis Approach
		10.5.4 Arm-Based IoT Malware Detection Using Byte Sequences from ELF Files
		10.5.5 ML Performance Evaluation Metrics
	10.6 Image-Based Zero-Day Malware Detection Using Deep Transfer Learning
		10.6.1 Dataset Characteristics
		10.6.2 Threat Model: Zero-Day Malware Detection
		10.6.3 Feature Engineering
			10.6.3.1 Feature Engineering Workflow
			10.6.3.2 Feature Normalization
			10.6.3.3 Feature Importance Analysis
			10.6.3.4 Feature Correlations Analysis
			10.6.3.5 Feature Selection
		10.6.4 Standard ML-Based Malware Detectors
		10.6.5 Advanced Framework: Image-Based Deep Transfer Learning-Enabled Method: Deep-HMD
			10.6.5.1 Transfer Learning Approach
			10.6.5.2 Embedding Tabular Data to Images
			10.6.5.3 Training and Testing of ML Detector
		10.6.6 Experimental Results and Evaluation
	10.7 Conclusion
	References
11 Machine Learning Applications and Attacks Using Side Channel Analysis
	11.1 Introduction
	11.2 Machine Learning Overview
		11.2.1 Supervised Machine Learning
		11.2.2 Unsupervised Machine Learning
		11.2.3 Deep Learning Concepts
	11.3 Side Channel Attacks
		11.3.1 Power and EM Analysis
			11.3.1.1 Simple Power Analysis
			11.3.1.2 Differential Power Analysis
			11.3.1.3 Correlation Power Analysis
		11.3.2 ML Attacks on Power and EM
		11.3.3 Direct Memory Access (DMA) as a Side Channel Attack
		11.3.4 ML Attacks on DMA
	11.4 Side Channel Attacks on ML Models
	11.5 Novel AI-Based Countermeasures
	11.6 Side Channel Attacks for Post-quantum Cryptography
	11.7 Conclusion
	References
12 Adapt and Defend: Reinforcement Learning for Hardware-Assisted Security
	12.1 Malware Detection Techniques: Background and Taxonomy
		12.1.1 Misuse-Based Malware Detection
		12.1.2 Anomaly-Based Malware Detection
	12.2 Hardware-Assisted Cybersecurity: ML-Enabled Malware Detection Using Hardware Features
	12.3 ML-Assisted Malware Detection: Overview and Procedure
	12.4 Feature Engineering: Analysis of Key Features
		12.4.1 Correlation Attribute Evaluation (CAE)
		12.4.2 Principal Component Analysis (PCA)
		12.4.3 Gain Ratio Evaluation (GRE)
		12.4.4 Fisher Score (FS)
			12.4.4.1 Comparative Analysis of Feature Selection Techniques
	12.5 Machine-Learning-Based Self-adaptive System
	12.6 Reinforcement Learning: An Overview
	12.7 Reinforcement Learning Agents
		12.7.1 Multiarmed Bandit: Upper Confidence Bound
		12.7.2 Temporal-Difference Learning: Q-Learning
		12.7.3 Value Approximation Method: Dueling DQN
		12.7.4 Policy Gradient Method: Advantage Actor Critic
	12.8 Reinforcement Learning Environment
		12.8.1 OpenAI's RL Environment
	12.9 Adaptive RL-Guided Framework for Hardware-Assisted Security
		12.9.1 Dataset and Hardware Monitoring
		12.9.2 Methodology
			12.9.2.1 Feature Engineering
			12.9.2.2 Threat Model
			12.9.2.3 Training Phase
			12.9.2.4 RL Environment
			12.9.2.5 RL Agents
			12.9.2.6 Online Inference
		12.9.3 Experimental Results and Evaluation
			12.9.3.1 Effectiveness Analysis of Feature Fusion
			12.9.3.2 Base ML-Based Malware Detectors
			12.9.3.3 RL-Guided Self-adaptive Framework Evaluation: Learning Performance
			12.9.3.4 RL-Guided Self-adaptive Framework Evaluation: Accumulated Rewards for Zero-Day Test
			12.9.3.5 RL-Guided Self-adaptive Framework Evaluation: Performance vs. Cost-Efficiency Analysis Against State-of-the-Art ML Models
			12.9.3.6 RL-Guided Self-adaptive Framework Evaluation: Inference Overhead
	12.10 Conclusion
	References
13 Machine Learning-Enhanced Analysis and Design for Trustworthy Integrated Circuits
	13.1 Introduction
	13.2 Design-Time Methods and Tools: Circuit Obfuscation
		13.2.1 ML-Assisted Attacks on Logic Locking (Fig. 13.2)
			13.2.1.1 Oracle-Based Attacks
			13.2.1.2 Oracle-Less Attacks
		13.2.2 Defenses Against ML-Assisted Attacks on Logic Locking
		13.2.3 Discussion and Future Directions
	13.3 Test-Based Methods and Tools
		13.3.1 ML-Enhanced Hardware Trojan Detection (Table 13.1)
		13.3.2 Discussion and Future Directions
	13.4 ML-Enhanced Vulnerability Identification
		13.4.1 Hardware Fuzzing
			13.4.1.1 Traditional Fuzzing
			13.4.1.2 Integrating ML into Fuzzing
			13.4.1.3 Discussion and Future Directions
		13.4.2 IC Reverse Engineering
			13.4.2.1 ML-Enhanced IC Reverse Engineering
			13.4.2.2 Discussion and Future Directions
	13.5 IC Identifiers
		13.5.1 Physical Unclonable Function
		13.5.2 ML-Based Attacks on PUF (Table 13.2)
		13.5.3 Defenses Countering ML-Based Attacks on PUF
		13.5.4 Discussion and Future Directions
	13.6 Conclusion
	References
14 Hardware Accelerators for Artificial Intelligence
	14.1 Introduction to Hardware Accelerators for AI
		14.1.1 Overview of AI Advancements and Impacts
		14.1.2 AI Hardware Accelerators: Overcoming Traditional Limits
	14.2 AI Algorithms and Their Hardware Implementation
		14.2.1 Overview of Key AI Algorithms
		14.2.2 Case Studies of Hardware Accelerator for AI
		14.2.3 Comparative Analysis of Different Hardware Solutions for AI
	14.3 AI Hardware Accelerator Architectures
		14.3.1 NeuFlow Architecture
		14.3.2 The DianNao Series
		14.3.3 The Neural Processing Unit (NPU)
		14.3.4 RENO Architecture
		14.3.5 Neurocube Architecture
		14.3.6 PRIME: ReRAM-Based Processing-in-Memory Architecture
		14.3.7 Tensor Processing Unit (TPU)
		14.3.8 Eyeriss v2 Architecture
		14.3.9 RLC Compressed Form Architecture (CompAct)
	14.4 Design Considerations and Optimization Technique
		14.4.1 Design Considerations
		14.4.2 Optimization Techniques
			14.4.2.1 Architectural Optimization Techniques
			14.4.2.2 Emerging Technologies
			14.4.2.3 Impact of Optimization Techniques
	14.5 Applications and Future
		14.5.1 Revolutionizing Industries
		14.5.2 The Future of Hardware Accelerator
	14.6 -10pt
	References
15 Implementation of Associative Learning Using Cognitive-Inspired Robotic System
	15.1 Introduction
	15.2 Background
		15.2.1 Neuromorphic Computing
		15.2.2 Associative Learning
	15.3 Fear Conditioning with Cognitive-Inspired Robots
		15.3.1 Simulation and Preliminary Testing
			15.3.1.1 Experimental Validation
			15.3.1.2 Locally Competitive Algorithm
	15.4 Conclusion
	References
16 Enabling Memory-Augmented Neural Networks for Efficient Edge Applications
	16.1 Introduction
	16.2 Background
		16.2.1 Challenges and Optimization Techniques of Deploying Neural Networks on Edge Devices
		16.2.2 Posit Number System
		16.2.3 Quantization, Posit, and MANNs
	16.3 Memory-Augmented Neural Networks
		16.3.1 MANN Structure
		16.3.2 KV-MANN Structure
		16.3.3 Comparative Analysis and Challenges of MANN
	16.4 MANN Model Pruning
		16.4.1 A2P-MANN Method
	16.5 Posit MANN
	16.6 A2P-MANN and Posit MANN Evaluations
		16.6.1 Models and Datasets of the Study
		16.6.2 A2P-MANN Evaluation
		16.6.3 Partial Posit MANN Evaluation
		16.6.4 Full Posit MANN Evaluation
	16.7 Conclusion
	References
Index