Advances in VLSI and Embedded Systems: Select Proceedings of AVES 2019

Front Matter ....Pages i-xix
 Reusability and Scalability of an SoC Testbench in Mixed-Signal Verification—The Inevitable Necessity  (Babun Chandra Pal)....Pages 1-16
 Automated Simulator for the Validation of Bio-Impedance Devices  (S. Sruthi, Rasika Dhavse, Jignesh N. Sarvaiya)....Pages 17-30
 Analysis of Memory-Based Real Fast Fourier Transform Architectures for Low-Area Applications  (Rajasekhar Turaka, M. Satya Sai Ram)....Pages 31-39
 Optimization of MEMS-Based Capacitive Sensor with High-k Dielectric for Detection of Heavy Metal Ions  (Dinesh Rotake, Anand D. Darji)....Pages 41-53
 Statistical Analysis of Vehicle Detection in the ITS Application for Monitoring the Traffic and Road Accident Using Internet of Things  (Diya Vadhwani, Devendra Thakor)....Pages 55-70
 Qualitative and Quantitative Analysis of Parallel-Prefix Adders  (Sudhanshu Janwadkar, Rasika Dhavse)....Pages 71-88
 A Novel Method of Multiplication with Ekanyunena Purvena  (M. A. Sayyad, D. N. Kyatanavar)....Pages 89-96
 FPGA Design of SAR Type ADC Based Analog Input Module for Industrial Applications  (G. Dhanabalan, T. Murugan)....Pages 97-113
 Need for Predictive Data Analytics in Cold Chain Management  (Swati D. Kale, Shailaja C. Patil)....Pages 115-129
 FPGA-Based Implementation of Artifact Suppression and Feature Extraction  (Shrikant Kumbhar, Anand D. Darji, Harikrishna M. Singapuri)....Pages 131-143
 Test Time Reduction Using Power-Aware Dynamic Clock Allocation to Scan Vectors  (Harikrishna Parmar, Usha Mehta)....Pages 145-157
 Impact of Spacers in Raised Source/Drain 14 nm Technology Node In\\(_{0.53}\\)Ga\\(_{0.47}\\)As-nFinFET on Short Channel Effects  (Jay Pathak, Anand D. Darji)....Pages 159-167
 Impact of Multi-Metal Gate Stacks on the Performance of β-Ga2O3 MOS Structure  (Narendra Yadava, R. K. Chauhan)....Pages 169-174
 Improved VLSI Architecture of Dual-CLCG for Pseudo-Random Bit Generator  (Mangal Deep Gupta, R. K. Chauhan)....Pages 175-182
 Low Power Radix-8 Modulo \\(2^n+1\\) Multiplier Using Modified Weighted Method  (Naveen Kumar Kabra, Zuber M. Patel)....Pages 183-200
 Design of Prominent Single-Precision 32-Bit Floating-Point Adder Using Single-Electron Transistor Operating at Room Temperature  (Ankur Sharma, Rasika Dhavse, Yash Agrawal, Rutu Parekh)....Pages 201-209
 Image Communication Using Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) Code  (Dharmesh Jayantibhai Patel, Pinalkumar Engineer, Ninad Sunilkumar Bhatt)....Pages 211-221
 Smart Soldier Health Monitoring System Incorporating Embedded Electronics  (Krishna Teja, Umang Patel, Parthkumar Patel, Yash Agrawal, Rutu Parekh)....Pages 223-234
 A 3–7 GHz CMOS Power Amplifier Design for Ultra-Wide-Band Applications  (Vishakha Purnanand Bhale, Upena Dalal)....Pages 235-246
 An Approach to Detect and Prevent Distributed Denial of Service Attacks Using Blockchain Technology in Cloud Environment  (Vishwani Patel, Fenil Khatiwala, Yashi Choksi)....Pages 247-258
 Variability Analysis of On-Chip Interconnect System Using Prospective Neural Network  (Ajita Misra, Yash Agrawal, Vinay Palaparthy, Rutu Parekh)....Pages 259-271
 Prospective Incorporation of Booster in Carbon Interconnects for High-Speed Integrated Circuits  (Takshashila Pathade, Yash Agrawal, Rutu Parekh, Mekala Girish Kumar)....Pages 273-288
 Island Engineering of Single-Electron Transistor for Room Temperature Operation  (Raj Shah, Rutu Parekh, Rasika Dhavse)....Pages 289-299