Advanced Digital System Design: A Practical Guide to Verilog Based FPGA and ASIC Implementation

Preface\n	Objective of the Book\n	Organization of the Book\nAcknowledgements\nContents\nAbout the Author\nAbbreviations\n1 Binary Number System\n	1.1 Introduction\n	1.2 Binary Number System\n	1.3 Representation of Numbers\n		1.3.1 Signed Magnitude Representation\n		1.3.2 One\'s Complement Representation\n		1.3.3 Two\'s Complement Representation\n	1.4 Binary Representation of Real Numbers\n		1.4.1 Fixed Point Data Format\n	1.5 Floating Point Data Format\n	1.6 Signed Number System\n		1.6.1 Binary SD Number System\n		1.6.2 SD Representation to Two\'s Complement Representation\n	1.7 Conclusion\n2 Basics of Verilog HDL\n	2.1 Introduction\n	2.2 Verilog Expressions\n		2.2.1 Verilog Operands\n		2.2.2 Verilog Operators\n		2.2.3 Concatenation and Replication\n	2.3 Data Flow Modelling\n	2.4 Behavioural Modelling\n		2.4.1 Initial Statement\n		2.4.2 Always Statement\n		2.4.3 Timing Control\n		2.4.4 Procedural Assignment\n	2.5 Structural Modelling\n		2.5.1 Gate-Level Modelling\n		2.5.2 Hierarchical Modelling\n	2.6 Mixed Modelling\n	2.7 Verilog Function\n	2.8 Verilog Task\n	2.9 File Handling\n		2.9.1 Reading from a Text File\n		2.9.2 Writing into a Text File\n	2.10 Test Bench Writing\n	2.11 Frequently Asked Questions\n	2.12 Conclusion\n3 Basic Combinational Circuits\n	3.1 Introduction\n	3.2 Addition\n	3.3 Subtraction\n	3.4 Parallel Binary Adder\n	3.5 Controlled Adder/Subtractor\n	3.6 Multiplexers\n	3.7 De-Multiplexers\n	3.8 Decoders\n	3.9 Encoders\n	3.10 Majority Voter Circuit\n	3.11 Data Conversion Between Binary and Gray Code\n	3.12 Conversion Between Binary and BCD Code\n		3.12.1 Binary to BCD Conversion\n		3.12.2 BCD to Binary Conversion\n	3.13 Parity Generators/Checkers\n	3.14 Comparators\n	3.15 Constant Multipliers\n	3.16 Frequently Asked Questions\n	3.17 Conclusion\n4 Basic Sequential Circuits\n	4.1 Introduction\n	4.2 Different Flip-Flops\n		4.2.1 SR Flip-Flop\n		4.2.2 JK Flip-Flop\n		4.2.3 D Flip-Flop\n		4.2.4 T Flip-Flop\n		4.2.5 Master-Slave D Flip-Flop\n	4.3 Shift Registers\n		4.3.1 Serial In Serial Out\n		4.3.2 Serial In Parallel Out\n		4.3.3 Parallel In Serial Out\n		4.3.4 Parallel In Parallel Out\n	4.4 Sequence Generator\n	4.5 Pseudo Noise Sequence Generator\n	4.6 Synchronous Counter Design\n	4.7 Loadable Counter\n		4.7.1 Loadable Up Counter\n		4.7.2 Loadable Down Counter\n	4.8 Even and Odd Counter\n	4.9 Shift Register Counters\n	4.10 Phase Generation Block\n	4.11 Clock Divider Circuits\n		4.11.1 Clock Division by Power of 2\n		4.11.2 Clock Division by 3\n		4.11.3 Clock Division by 6\n		4.11.4 Programmable Clock Divider Circuit\n	4.12 Frequently Asked Questions\n	4.13 Conclusion\n5 Memory Design\n	5.1 Introduction\n	5.2 Controlled Register\n	5.3 Read Only Memory\n		5.3.1 Single Port ROM\n		5.3.2 Dual Port ROM (DPROM)\n	5.4 Random Access Memory (RAM)\n		5.4.1 Single Port RAM (SPRAM)\n		5.4.2 Dual Port RAM (DPRAM)\n	5.5 Memory Initialization\n	5.6 Implementing Bigger Memory Element Using Smaller Memory Elements\n	5.7 Implementation of Memory Elements\n	5.8 Conclusion\n6 Finite State Machines\n	6.1 Introduction\n	6.2 FSM Types\n	6.3 Sequence Detector Using Mealy Machine\n	6.4 Sequence Detector Using Moore Machine\n	6.5 Comparison of Mealy and Moore Machine\n	6.6 FSM-Based Serial Adder Design\n	6.7 FSM-Based Vending Machine Design\n	6.8 State Minimization Techniques\n	6.9 Row Equivalence Method\n	6.10 Implication Chart Method\n	6.11 State Partition Method\n	6.12 Performance of State Minimization Techniques\n	6.13 Verilog Modelling of FSM-Based Systems\n	6.14 Frequently Asked Questions\n	6.15 Conclusion\n7 Design of Adder Circuits\n	7.1 Introduction\n	7.2 Ripple Carry Adder\n	7.3 Carry Look-Ahead Adder\n		7.3.1 Higher Bit Adders Using CLA\n		7.3.2 Prefix Tree Adders\n	7.4 Manchester Carry Chain Module (MCC)\n	7.5 Carry Skip Adder\n	7.6 Carry Increment Adder\n	7.7 Carry Select Adder\n	7.8 Conditional Sum Adder\n	7.9 Ling Adders\n	7.10 Hybrid Adders\n	7.11 Multi-operand Addition\n		7.11.1 Carry Save Addition\n		7.11.2 Tree of Carry Save Adders\n	7.12 BCD Addition\n	7.13 Conclusion\n8 Design of Multiplier Circuits\n	8.1 Introduction\n	8.2 Sequential Multiplication\n	8.3 Array Multipliers\n	8.4 Partial Product Generation and Reduction\n		8.4.1 Booth\'s Multiplication\n		8.4.2 Radix-4 Booth\'s Algorithm\n		8.4.3 Canonical Recoding\n		8.4.4 An Alternate 2-bit at-a-time Multiplication Algorithm\n		8.4.5 Implementing Larger Multipliers Using Smaller Ones\n	8.5 Accumulation of Partial Products\n		8.5.1 Accumulation of Partial Products for Unsigned Numbers\n		8.5.2 Accumulation of Partial Products for Signed Numbers\n		8.5.3 Alternative Techniques for Partial Product Accumulation\n	8.6 Wallace and Dedda Multiplier Design\n	8.7 Multiplication Using Look-Up Tables\n	8.8 Dedicated Square Block\n	8.9 Architectures Based on VEDIC Arithmetic\n		8.9.1 VEDIC Multiplier\n		8.9.2 VEDIC Square Block\n		8.9.3 VEDIC Cube Block\n	8.10 Conclusion\n9 Division and Modulus Operation\n	9.1 Introduction\n	9.2 Sequential Division Methods\n		9.2.1 Restoring Division\n		9.2.2 Unsigned Array Divider\n		9.2.3 Non-restoring Division\n		9.2.4 Conversion from Signed Binary to Two\'s Complement\n	9.3 Fast Division Algorithms\n		9.3.1 SRT Division\n		9.3.2 SRT Algorithm Properties\n	9.4 Iterative Division Algorithms\n		9.4.1 Goldschmidt Division\n		9.4.2 Newton–Raphson Division\n	9.5 Computation of Modulus\n	9.6 Conclusion\n10 Square Root and its Reciprocal\n	10.1 Introduction\n	10.2 Slow Square Root Computation Methods\n		10.2.1 Restoring Algorithm\n		10.2.2 Non-restoring Algorithm\n	10.3 Iterative Algorithms for Square Root and its Reciprocal\n		10.3.1 Goldschmidt Algorithm\n		10.3.2 Newton–Raphson Iteration\n		10.3.3 Halley\'s Method\n		10.3.4 Bakhshali Method\n		10.3.5 Two Variable Iterative Method\n	10.4 Fast SRT Algorithm for Square Root\n	10.5 Taylor Series Expansion Method\n		10.5.1 Theory\n		10.5.2 Implementation\n	10.6 Function Evaluation by Bipartite Table Method\n	10.7 Conclusion\n11 CORDIC Algorithm\n	11.1 Introduction\n	11.2 Theoretical Background\n	11.3 Vectoring Mode\n		11.3.1 Computation of Sine and Cosine\n	11.4 Linear Mode\n		11.4.1 Multiplication\n		11.4.2 Division\n	11.5 Hyperbolic Mode\n		11.5.1 Square Root Computation\n	11.6 CORDIC Algorithm Using Redundant Number System\n		11.6.1 Redundant Radix-2-Based CORDIC Algorithm\n		11.6.2 Redundant Radix-4-Based CORDIC Algorithm\n	11.7 Example of CORDIC Iteration\n	11.8 Implementation of CORDIC Algorithms\n		11.8.1 Parallel Architecture\n		11.8.2 Serial Architecture\n		11.8.3 Improved CORDIC Architectures\n	11.9 Application\n	11.10 Conclusion\n12 Floating Point Architectures\n	12.1 Introduction\n	12.2 Floating Point Representation\n	12.3 Fixed Point to Floating Point Conversion\n	12.4 Leading Zero Counter\n	12.5 Floating Point Addition\n	12.6 Floating Point Multiplication\n	12.7 Floating Point Division\n	12.8 Floating Point Comparison\n	12.9 Floating Point Square Root\n	12.10 Floating Point to Fixed Point Conversion\n	12.11 Conclusion\n13 Timing Analysis\n	13.1 Introduction\n	13.2 Timing Definitions\n		13.2.1 Slew of Waveform\n		13.2.2 Clock Jitter\n		13.2.3 Clock Latency\n		13.2.4 Launching and Capturing Flip-Flop\n		13.2.5 Clock Skew\n		13.2.6 Clock Uncertainty\n		13.2.7 Clock-to-Q Delay\n		13.2.8 Combinational Logic Timing\n		13.2.9 Min and Max Timing Paths\n		13.2.10 Clock Domains\n		13.2.11 Setup Time\n		13.2.12 Hold Time\n		13.2.13 Slack\n		13.2.14 Required Time and Arrival Time\n		13.2.15 Timing Paths\n	13.3 Timing Checks\n		13.3.1 Setup Timing Check\n		13.3.2 Hold Timing Check\n	13.4 Timing Checks for Different Timing Paths\n		13.4.1 Setup Check for Flip-Flop to Flip-Flop Timing Path\n		13.4.2 Setup and Hold Check for Input to Flip-Flop Timing Path\n		13.4.3 Setup Check for Flip-Flop to Output Timing Path\n		13.4.4 Setup Check for Input to Output Timing Path\n		13.4.5 Multicycle Paths\n		13.4.6 False Paths\n		13.4.7 Half Cycle Paths\n	13.5 Asynchronous Checks\n		13.5.1 Recovery Timing Check\n		13.5.2 Removal Timing Check\n	13.6 Maximum Frequency Computation\n	13.7 Maximum Allowable Skew\n	13.8 Frequently Asked Questions\n	13.9 Conclusion\n14 Digital System Implementation\n	14.1 Introduction\n	14.2 FPGA Implementation\n		14.2.1 Internal Structure of FPGA\n		14.2.2 FPGA Implementation Using XILINX EDA Tool\n		14.2.3 Design Verification\n		14.2.4 FPGA Editor\n	14.3 ASIC Implementation\n		14.3.1 Simulation and Synthesis\n		14.3.2 Placement and Routing\n	14.4 Frequently Asked Questions\n	14.5 Conclusion\n15 Low-Power Digital System Design\n	15.1 Introduction\n	15.2 Different Types of Power Consumption\n		15.2.1 Switching Power\n		15.2.2 Short Circuit Power\n		15.2.3 Leakage Power\n		15.2.4 Static Power\n	15.3 Architecture-Driven Voltage Scaling\n		15.3.1 Serial Architecture\n		15.3.2 Parallel Architecture\n		15.3.3 Pipeline Architecture\n	15.4 Algorithmic Optimization\n		15.4.1 Minimizing the Hardware Complexity\n		15.4.2 Selection of Data Representation Techniques\n	15.5 Architectural Optimization\n		15.5.1 Choice of Data Representation Techniques\n		15.5.2 Ordering of Input Signals\n		15.5.3 Reducing Glitch Activity\n		15.5.4 Choice of Topology\n		15.5.5 Logic Level Power Down\n		15.5.6 Synchronous Versus Asynchronous\n		15.5.7 Loop Unrolling\n		15.5.8 Operation Reduction\n		15.5.9 Substitution of Operation\n		15.5.10 Re-timing\n		15.5.11 Wordlength Reduction\n		15.5.12 Resource Sharing\n	15.6 Frequently Asked Questions\n	15.7 Conclusion\n16 Digital System Design Examples\n	16.1 FPGA Implementation FIR Filters\n		16.1.1 FIR Low-Pass Filter\n		16.1.2 Advanced DSP Blocks\n		16.1.3 Different Filter Structures\n		16.1.4 Performance Estimation\n		16.1.5 Conclusion\n		16.1.6 Top Module for FIR Filter in Transposed Direct Form\n	16.2 FPGA Implementation of IIR Filters\n		16.2.1 IIR Low-Pass Filter\n		16.2.2 Different IIR Filter Structures\n		16.2.3 Pipeline Implementation of IIR Filters\n		16.2.4 Performance Estimation\n		16.2.5 Conclusion\n	16.3 FPGA Implementation of K-Means Algorithm\n		16.3.1 K-Means Algorithm\n		16.3.2 Example of K-Means Algorithm\n		16.3.3 Proposed Architecture\n		16.3.4 Design Performance\n		16.3.5 Conclusion\n	16.4 Matrix Multiplication\n		16.4.1 Matrix Multiplication by Scalar–Vector Multiplication\n		16.4.2 Matrix Multiplication by Vector–Vector Multiplication\n		16.4.3 Systolic Array for Matrix Multiplication\n	16.5 Sorting Architectures\n		16.5.1 Parallel Sorting Architecture 1\n		16.5.2 Parallel Sorting Architecture 2\n		16.5.3 Serial Sorting Architecture\n		16.5.4 Sorting Processor Design\n	16.6 Median Filter for Image De-noising\n		16.6.1 Median Filter\n		16.6.2 FPGA Implementation of Median Filter\n	16.7 FPGA Implementation of 8-Point FFT\n		16.7.1 Data Path for 8-Point FFT Processor\n		16.7.2 Control Path for 8-Point FFT Processor\n	16.8 Interfacing ADC Chips with FPGA Using SPI Protocol\n	16.9 Interfacing DAC Chips with FPGA Using SPI Protocol\n	16.10 Interfacing External Devices with FPGA Using UART\n	16.11 Conclusion\n17 Basics of System Verilog\n	17.1 Introduction\n	17.2 Language Elements\n		17.2.1 Logic Literal Values\n		17.2.2 Basic Data Types\n		17.2.3 User Defined Data-Types\n		17.2.4 Enumeration Data Type\n		17.2.5 Arrays\n		17.2.6 Dynamic Arrays\n		17.2.7 Associative Array\n		17.2.8 Queues\n		17.2.9 Events\n		17.2.10 String Methods\n	17.3 Composite Data Types\n		17.3.1 Structures\n		17.3.2 Unions\n		17.3.3 Classes\n	17.4 Expressions\n		17.4.1 Parameters and Constants\n		17.4.2 Variables\n		17.4.3 Operators\n		17.4.4 Set Membership Operator\n		17.4.5 Static Cast Operator\n		17.4.6 Dynamic Casting\n		17.4.7 Type Operator\n		17.4.8 Concatenation of String Data Type\n		17.4.9 Streaming Operators\n	17.5 Behavioural Modelling\n		17.5.1 Procedural Constructs\n		17.5.2 Loop Statements\n		17.5.3 Case Statement\n		17.5.4 If Statement\n		17.5.5 Final Statement\n		17.5.6 Disable Statement\n		17.5.7 Event Control\n		17.5.8 Continuous Assignment\n		17.5.9 Parallel Blocks\n		17.5.10 Process Control\n	17.6 Structural Modelling\n		17.6.1 Module Prototype\n	17.7 Summary\n18 Advanced FPGA Implementation Techniques\n	18.1 Introduction\n	18.2 System-On-Chip Implementation\n		18.2.1 Implementations Using SoC FPGAs\n		18.2.2 AXI Protocol\n		18.2.3 AXI Protocol Features\n	18.3 Partial Re-configuration (PR)\n		18.3.1 Dynamic PR\n		18.3.2 Advantages of DPR\n		18.3.3 DPR Techniques\n		18.3.4 DPR Terminology\n		18.3.5 DPR Tools\n		18.3.6 DPR Flow\n		18.3.7 Communication Between Reconfigurable Modules\n	18.4 Conclusion\nAppendix  References\nIndex