VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Revised Selected Papers

Front Matter ....Pages i-xvi
Front Matter ....Pages 1-1
 Automations and Methodologies for Efficient and Quality Conscious Analog Layout Implementation  (Varun Kumar Dwivedi, Madhvi Sharma, Chandaka Venu)....Pages 3-13
 A 2.4 GHz High Efficiency Capacitive Cross Coupled Common Gate Class-E Differential Power Amplifier  (Archana Sunitha, Bhaskar Manickam)....Pages 14-22
 A 1.25–20 GHz Wide Tuning Range Frequency Synthesis for 40-Gb/s SerDes Application  (Javed S. Gaggatur, Abhishek Chaturvedi)....Pages 23-35
 Analyzing Design Parameters of Nano-Magnetic Technology Based Converter Circuit  (Bandan Kumar Bhoi, Neeraj Kumar Misa, Shailesh Singh Chouhan, Sarthak Acharya)....Pages 36-46
 Design of Current Mode Sigmoid Function and Hyperbolic Tangent Function  (Debanjana Datta, Sweta Agarwal, Vikash Kumar, Mayank Raj, Baidyanath Ray, Ayan Banerjee)....Pages 47-60
 Flexible Adaptive FIR Filter Designs Using LMS Algorithm  (M. Mohamed Asan Basiri)....Pages 61-71
 An Efficient Test and Fault Tolerance Technique for Paper-Based DMFB  (Chandan Das, Sarit Chakraborty, Susanta Chakraborty)....Pages 72-86
 A Generalized Technique of Automated Pin Sharing on Hexagonal Electrode Based Digital Microfluidic Biochip Along with Its Design Methodology  (Amartya Dutta, Riya Majumder, Debasis Dhal, Rajat Kumar Pal)....Pages 87-101
 A Space Efficient Greedy Droplet Routing for Digital Microfluidics Biochip  (Jyotiranjan Swain, Kolluri Rajesh, Sumanta Pyne)....Pages 102-114
 Design of 635 MHz Bandpass Filter Using High-Q Floating Active Inductor  (Aditya Kumar Hota, Kabiraj Sethi)....Pages 115-125
 Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology  (Saroja V. Siddamal, Suhas B. Shirol, Shraddha Hiremath, Nalini C. Iyer)....Pages 126-140
 Clock Pulse Based Foreground Calibration of a Sub-Radix-2 Successive Approximation Register ADC  (M. Mahendra Reddy, Sounak Roy)....Pages 141-149
 Approximate Computing Based Adder Design for DWT Application  (Moumita Acharya, Samik Basu, Biranchi Narayan Behera, Amlan Chakrabarti)....Pages 150-163
 An Efficient Wireless Charging Technique Using Inductive and Resonant Circuits  (Purvi Agrawal, Ruchi Dhamnani, Ananya Garg, Shrivishal Tripathi, Manoj Kumar Majumder)....Pages 164-170
 A Novel Gate-Level On-Chip Crosstalk Noise Reduction Circuit for Deep Sub-micron Technology  (Swatilekha Majumdar)....Pages 171-179
 On-Chip Threshold Compensated Voltage Doubler for RF Energy Harvesting  (Arun Mohan, Saroj Mondal, Surya Shankar Dan)....Pages 180-189
 Utilizing NBTI for Operation Detection of Integrated Circuits  (Ambika Prasad Shah, Amirhossein Moshrefi, Michael Waltl)....Pages 190-201
 A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS  (Raviteja Kammari, Vijaya Sankara Rao Pasupureddi)....Pages 202-214
 A CMOS Low Noise Amplifier with Improved Gain  (Sunanda Ambulker, Jitendra Kumar Mishra, Sangeeta Nakhate)....Pages 215-223
 Radiation Hardened by Design Sense Amplifier  (Avinash Verma, Gaurav Kaushal)....Pages 224-235
 Delay Efficient All Optical Carry Lookahead Adder  (Sayantani Roy, Arighna Deb, Debesh K. Das)....Pages 236-244
Front Matter ....Pages 245-245
 Asynchronous Hardware Design for Floating Point Multiply-Accumulate Circuit  (M. Mohamed Asan Basiri)....Pages 247-257
 A Unified Methodology for Hardware Obfuscation and IP Watermarking  (Saurabh Gangurde, Binod Kumar)....Pages 258-271
 Threshold Implementation of a Low-Cost CLEFIA-128 Cipher for Power Analysis Attack Resistance  (S. Shanthi Rekha, P. Saravanan)....Pages 272-285
 Brain Inspired One Shot Learning Method for HD Computing  (Devika R. Nair, A. Purushothaman)....Pages 286-297
 Dual-Edge Triggered Lightweight Implementation of AES for IoT Security  (Sajid Khan, Neha Gupta, Abhinav Vishvakarma, Shailesh Singh Chouhan, Jai Gopal Pandey, Santosh Kumar Vishvakarma)....Pages 298-307
 2L-2D Routing for Buffered Mesh Network-on-Chip  (Rose George Kunthara, K. Neethu, Rekha K. James, Simi Zerine Sleeba, Tripti S. Warrier, John Jose)....Pages 308-320
 Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network  (Gopal Raut, Vishal Bhartiy, Gunjan Rajput, Sajid Khan, Ankur Beohar, Santosh Kumar Vishvakarma)....Pages 321-333
 An Ultra Low Power AES Architecture for IoT  (Sajid Khan, Neha Gupta, Gopal Raut, Gunjan Rajput, Jai Gopal Pandey, Santosh Kumar Vishvakarma)....Pages 334-344
 Efficient Closely-Coupled Integration of AES Coprocessor with LEON3 Processor  (Rajul Bansal, Abhijit Karmakar)....Pages 345-356
 Investigating the Role of Parasitic Resistance in a Class of Nanoscale Interconnects  (Shah Zahid Yousuf, Anil Kumar Bhardwaj, Rohit Sharma)....Pages 357-370
 A True Single-Phase Error Masking Flip-Flop with Reduced Clock Power for Near-Threshold Designs  (Priyamvada Sharma, Bishnu Prasad Das)....Pages 371-382
Front Matter ....Pages 383-383
 ASIC Based LVDT Signal Conditioner for High-Accuracy Measurements  (K. P. Raghunath, K. V. Manu Sagar, T. Gokulan, Kundan Kumar, Chetan Singh Thakur)....Pages 385-397
 Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard  (Neelam Arya, Anil Kumar Rajput, Manisha Pattanaik, G. K. Sharma)....Pages 398-412
 Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods  (V. S. Vineesh, Binod Kumar, Jay Adhaduk)....Pages 413-427
 Comparative Analysis of Logic Gates Based on Spin Transfer Torque (STT) and Differential Spin Hall Effect (DSHE) Switching Mechanisms  (Piyush Tankwal, Vikas Nehra, Brajesh Kumar Kaushik)....Pages 428-441
 Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture  (P. Veda Bhanu, Pranav V. Kulkarni, Sai Pranavi Avadhanam, J. Soumya, Linga Reddy Cenkeramaddi)....Pages 442-454
 A Realistic Configurable Level Triggered Flip-Flop in Quantum-Dot Cellular Automata  (Mrinal Goswami, Mayukh Roy Choudhury, Bibhash Sen)....Pages 455-467
 User Guided Register Manipulation in Digital Circuits  (Priyanka Panigrahi, Rajesh Kumar Jha, Chandan Karfa)....Pages 468-481
 RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor  (Aneesh Raveendran, Sandra Jean, J. Mervin, D. Vivian, David Selvakumar)....Pages 482-495
 Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU  (Aneesh Raveendran, Vinay Kumar, D. Vivian, David Selvakumar)....Pages 496-509
 Real Time Implementation of Convolutional Neural Network to Detect Plant Diseases Using Internet of Things  (Govind Bajpai, Aniket Gupta, Nitanshu Chauhan)....Pages 510-522
 A Novel 20nm FinFET Based 10T SRAM Cell Design for Improved Performance  (Anushka Singh, Yash Sharma, Arvind Sharma, Archana Pandey)....Pages 523-531
 Design of a Power Efficient Pulse Latch Circuit as a Solution for Master Slave Flip-Flop  (Muneeb Sulthan, Shubhajit Roy Chowdury, Rajnish Garg, Alok Tripathi)....Pages 532-540
 Design and Analysis for Power Reduction with High SNM of 10T SRAM Cell  (Kamini Singh, R. S. Gamad, P. P. Bansod)....Pages 541-549
Front Matter ....Pages 551-551
 A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF Applications  (Kanika Monga, Nitin Chaturvedi)....Pages 553-564
 Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models  (Deepthi Amuru, Andleeb Zahra, Zia Abbas)....Pages 565-578
 A Novel Design of SRAM Using Memristors at 45 nm Technology  (V. Jeffry Louis, Jai Gopal Pandey)....Pages 579-589
 Design and Calibration of 14-bit 10 KS/s Low Power SAR ADC for Bio-medical Applications  (Yadukrishnan Mekkattillam, Satyajit Mohapatra, Nihar R. Mohapatra)....Pages 590-604
 An Approach for Detection of Node Displacement Fault (NDF) in Reversible Circuit  (Bappaditya Mondal, Anirban Bhattacharjee, Subham Saha, Shalini Parekh, Chandan Bandyopadhyay, Hafizur Rahaman)....Pages 605-616
 Novel Approach for Improved Signal Integrity and Power Dissipation Using MLGNR Interconnects  (Vijay Rao Kumbhare, Punya Prasanna Paltani, Manoj Kumar Majumder)....Pages 617-629
 A Robust Low-Power Write-Assist Data-Dependent-Power-Supplied 12T SRAM Cell  (Neha Gupta, Jitesh Prasad, Rana Sagar Kumar, Gunjan Rajput, Santosh Kumar Vishvakarma)....Pages 630-642
 Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell  (Neha Gupta, Tanisha Gupta, Sajid Khan, Abhinav Vishwakarma, Santosh Kumar Vishvakarma)....Pages 643-654
 Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications  (Ankur Beohar, Gopal Raut, Gunjan Rajput, Abhinav Vishwakarma, Ambika Prasad Shah, Bhupendra Singh Renewal et al.)....Pages 655-663
Front Matter ....Pages 665-665
 Compact Modeling of Drain-Extended MOS Transistor Using BSIM-BULK Model  (Shivendra Singh Parihar, Ramchandra Gurjar)....Pages 667-678
 Technology Characterization Model and Scaling for Energy Management  (Harshil Goyal, Vishwani D. Agrawal)....Pages 679-693
 GaAs-SiGe Based Novel Device Structure of Doping Less Tunnel FET  (Shivendra Yadav, Chithraja Rajan, Dheeraj Sharma, Sanjay Balotiya)....Pages 694-701
 Performance Modelling and Dynamic Scheduling on Heterogeneous-ISA Multi-core Architectures  (Nirmal Kumar Boran, Dinesh Kumar Yadav, Rishabh Iyer)....Pages 702-715
 Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain Underlap  (Venkata Appa Rao Yempada, Srivatsava Jandhyala)....Pages 716-726
 Low-Voltage Dual-Gate Organic Thin Film Transistors with Distinctly Placed Source and Drain  (Shagun Pal, Brijesh Kumar)....Pages 727-738
Front Matter ....Pages 739-739
 A Latency and Throughput Efficient Successive Cancellation Decoding of Polar Codes  (Sistla Lakshmi Manasa, G. Lakshmi Narayanan)....Pages 741-748
 All-Digital CMOS On-Chip Temperature Sensor with Time-Assisted Analytical Model  (Ankur Pokhara, Biswajit Mishra, Purvi Patel)....Pages 749-763
 Intelligent Traffic Light Controller: A Solution for Smart City Traffic Problem  (Anam Sabir, Anushree Jain, Yashwini Nathwani, Vaibhav Neema)....Pages 764-772
Back Matter ....Pages 773-775