VLSI Circuit Design Methodology Demystified: A Conceptual Taxonomy

VLSI Circuit Design Methodology Demystified......Page 3
Contents......Page 9
Foreword......Page 13
Foreword......Page 15
Preface......Page 17
Acknowledgments......Page 19
1. What is a chip?......Page 21
2. What are the requirements of a successful chip design?......Page 23
3. What are the challenges in today’s very deep submicron (VDSM), multimillion gate designs?......Page 24
4. What major process technologies are used in today’s design environment?......Page 25
5. What are the goals of new chip design?......Page 28
6. What are the major approaches of today’s very large scale integration (VLSI) circuit design practices?......Page 29
7. What is standard cell-based, application-specific integrated circuit (ASIC) design methodology?......Page 31
8. What is the system-on-chip (SoC) approach?......Page 32
10. What are the major tasks in developing a SoC chip from concept to silicon?......Page 35
11. What are the major costs of developing a chip?......Page 36
12. What are the major process steps in building MOSFET transistors?......Page 37
13. What are the two types of MOSFET transistors?......Page 39
14. What are base layers and metal layers?......Page 40
15. What are wafers and dies?......Page 44
16. What is semiconductor lithography?......Page 48
17. What is a package?......Page 53
18. What is the role of functional verification in the IC design process?......Page 61
19. What are some of the design integrity issues?......Page 64
20. What is design for testability?......Page 66
21. Why is reducing the chip’s power consumption so important?......Page 68
22. What are some of the challenges in chip packaging?......Page 69
23. What are the advantages of design reuse?......Page 70
24. What is hardware/software co-design?......Page 71
25. Why is the clock so important?......Page 74
26. What is the leakage current problem?......Page 77
27. What is design for manufacturability?......Page 80
28. What is chip reliability?......Page 82
29. What is analog integration in the digital environment?......Page 85
30. What is the role of EDA tools in IC design?......Page 87
31. What is the role of the embedded processor in the SoC environment?......Page 89
32. What are the major tasks and personnel required in a chip design project?......Page 93
33. What are the major steps in ASIC chip construction?......Page 94
34. What is the ASIC design flow?......Page 95
35. What are the two major aspects of ASIC design flow?......Page 97
36. What are the characteristics of good design flow?......Page 100
37. What is the role of market research in an ASIC project?......Page 101
38. What is the optimal solution of an ASIC project?......Page 102
39. What is system-level study of a project?......Page 104
40. What are the approaches for verifying design at the system level?......Page 105
41. What is register-transfer-level (RTL) system-level description?......Page 106
42. What are methods of verifying design at the register-transfer-level?......Page 107
43. What is a test bench?......Page 108
45. What is functional coverage?......Page 109
46. What is bug rate convergence?......Page 110
47. What is design planning?......Page 111
49. What is hardware description language (HDL)?......Page 112
50. What is register-transfer-level (RTL) description of hardware?......Page 113
51. What is standard cell? What are the differences among standard cell, gate-array, and sea-of-gate approaches?......Page 114
52. What is an ASIC library?......Page 123
53. What is logic synthesis?......Page 125
54. What are the optimization targets of logic synthesis?......Page 126
55. What is schematic or netlist?......Page 127
57. What is the purpose of test insertion during logic synthesis?......Page 131
58. What is the most commonly used model in VLSI circuit testing?......Page 132
59. What are controllability and observability in a digital circuit?......Page 134
60. What is a testable circuit?......Page 135
61. What is the aim of scan insertion?......Page 136
62. What is fault coverage? What is defect part per million (DPPM)?......Page 137
63. Why is design for testability important for a product’s financial success?......Page 139
64. What is chip power usage analysis?......Page 140
65. What are the major components of CMOS power consumption?......Page 141
67. What is VLSI physical design?......Page 143
68. What are the problems that make VLSI physical design so challenging?......Page 144
69. What is floorplanning?......Page 148
70. What is the placement process?......Page 151
71. What is the routing process?......Page 153
72. What is a power network?......Page 155
73. What is clock distribution?......Page 159
74. What are the key requirements for constructing a clock tree?......Page 163
75. What is the difference between time skew and length skew in a clock tree?......Page 165
76. What is scan chain?......Page 169
77. What is scan chain reordering?......Page 171
78. What is parasitic extraction?......Page 172
79. What is delay calculation?......Page 175
81. What kind of signal integrity problems do place and route tools handle?......Page 176
82. What is cross-talk delay?......Page 177
83. What is cross-talk noise?......Page 178
84. What is IR drop?......Page 179
86. What is gate-level logic verification before tapeout?......Page 182
87. What is equivalence check?......Page 183
88. What is timing verification?......Page 184
90. What is static timing analysis (STA)?......Page 185
91. What is simulation approach on timing verification?......Page 189
92. What is the logical-effort-based timing closure approach?......Page 193
93. What is physical verification?......Page 198
94. What are design rule check (DRC), design verification (DV), and geometry verification (GV)?......Page 199
95. What is schematic verification (SV) or layout versus schematic (LVS)?......Page 201
96. What is automatic test pattern generation (ATPG)?......Page 202
98. What is yield?......Page 204
99. What are the qualities of a good IC implementation designer?......Page 207
Conclusion......Page 209
Acronyms......Page 211
Bibliography......Page 215
Index......Page 219