VHDL for engineers

Cover......Page 1
Title......Page 2
Content......Page 6
List of Figures......Page 12
List of Programs......Page 20
Preface......Page 26
 1.1 VHDL/PLD Design Methodology......Page 34
 1.2 Requirements Analysis and Specification......Page 38
 1.3 VHDL Design Description......Page 39
 1.4 Verification Using Simulation......Page 44
 1.5 Testbenches......Page 46
 1.6 Functional (Behavioral) Simulation......Page 49
 1.7 Programmable Logic Devices (PLDs)......Page 51
 1.8 SPLDs and the 22V10......Page 54
 1.9 Logic Synthesis for the Target PLD......Page 60
 1.10 Place-and-Route and Timing Simulation......Page 64
 1.11 Programming and Verifying a Target PLD......Page 70
 1.12 VHDL/PLD Design Methodology Advantages......Page 71
 1.14 VHDL for Synthesis versus VHDL for Simulation......Page 72
 1.15 This Book’s Primary Objective......Page 73
 2.1 Design Units, Library Units, and Design Entities......Page 77
 2.2 Entity Declaration......Page 78
 2.3 VHDL Syntax Definitions......Page 80
 2.4 Port Modes......Page 83
 2.5 Architecture Body......Page 86
 2.6 Coding Styles......Page 88
 2.7 Synthesis Results versus Coding Style......Page 99
 2.8 Levels of Abstraction and Synthesis......Page 102
 2.9 Design Hierarchy and Structural Style......Page 104
 3.1 Object Classes and Object Types......Page 115
 3.2 Signal Objects......Page 117
 3.3 Scalar Types......Page 121
 3.4 Type Std_Logic......Page 126
 3.5 Scalar Literals and Scalar Constants......Page 132
 3.6 Composite Types......Page 133
 3.7 Arrays......Page 134
 3.8 Types Unsigned and Signed......Page 140
 3.9 Composite Literals and Composite Constants......Page 143
 3.10 Integer Types......Page 145
 3.11 Port Types for Synthesis......Page 149
 3.12 Operators and Expressions......Page 151
 4.1 Logical Operators......Page 156
 4.2 Signal Assignments in Dataflow Style Architectures......Page 160
 4.3 Selected Signal Assignment......Page 163
 4.4 Type Boolean and the Relational Operators......Page 165
 4.5 Conditional Signal Assignment......Page 167
 4.6 Priority Encoders......Page 172
 4.7 Don’t Care Inputs and Outputs......Page 173
 4.8 Decoders......Page 177
 4.9 Table Lookup......Page 180
 4.10 Three-state Buffers......Page 184
 4.11 Avoiding Combinational Loops......Page 188
 5.1 Behavioral Style Architecture......Page 198
 5.2 Process Statement......Page 202
 5.3 Sequential Statements......Page 203
 5.4 Case Statement......Page 204
 5.5 If Statement......Page 209
 5.6 Loop Statement......Page 214
 5.7 Variables......Page 218
 5.8 Parity Detector Example......Page 221
 5.9 Synthesis of Processes Describing Combinational Systems......Page 226
 6.1 Simulator Approaches......Page 234
 6.2 Elaboration......Page 236
 6.3 Signal Drivers......Page 241
 6.4 Simulator Kernel Process......Page 243
 6.5 Simulation Initialization......Page 245
 6.6 Simulation Cycles......Page 248
 6.7 Signals versus Variables......Page 256
 6.8 Delta Delays......Page 263
 6.9 Delta Delays and Combinational Feedback......Page 268
 6.10 Multiple Drivers......Page 272
 6.11 Signal Attributes......Page 274
 7.1 Design Verification......Page 284
 7.3 A Simple Testbench......Page 288
 7.4 Physical Types......Page 291
 7.5 Single Process Testbench......Page 293
 7.6 Wait Statements......Page 296
 7.7 Assertion and Report Statements......Page 298
 7.8 Records and Table Lookup Testbenches......Page 301
 7.9 Testbenches That Compute Stimulus and Expected Results......Page 305
 7.10 Predefined Shift Operators......Page 307
 7.11 Stimulus Order Based on UUT Functionality......Page 309
 7.12 Comparing a UUT to a Behavioral Intent Model......Page 312
 7.13 Code Coverage and Branch Coverage......Page 314
 7.14 Post-Synthesis and Timing Verifications for CombinationalDesigns......Page 317
 7.15 Timing Models Using VITAL and SDF......Page 321
 8.1 Sequential Systems and Their Memory Elements......Page 337
 8.2 D Latch......Page 341
 8.3 Detecting Clock Edges......Page 348
 8.4 D Flip-flops......Page 350
 8.5 Enabled (Gated) Flip-flop......Page 357
 8.6 Other Flip-flop Types......Page 361
 8.7 PLD Primitive Memory Elements......Page 364
 8.8 Timing Requirements and Synchronous Input Data......Page 365
 9.1 Multibit Latches and Registers......Page 370
 9.2 Shift Registers......Page 373
 9.3 Shift Register Counters......Page 379
 9.4 Counters......Page 381
 9.5 Detecting Non-clock Signal Edges......Page 393
 9.6 Microprocessor Compatible Pulse Width Modulated SignalGenerator......Page 399
 9.7 Memories......Page 403
 10.1 Finite State Machines......Page 413
 10.2 FSM State Diagrams......Page 419
 10.3 Three Process FSM VHDL Template......Page 421
 10.4 State Diagram Development......Page 425
 10.5 Decoder for an Optical Shaft Encoder......Page 436
 10.6 State Encoding and State Assignment......Page 442
 10.7 Supposedly Safe FSMs......Page 447
 10.8 Inhibit Logic FSM Example......Page 451
 11.1 Algorithmic State Machine Charts......Page 464
 11.2 Converting ASM Charts to VHDL......Page 471
 11.3 System Architecture......Page 474
 11.4 Successive Approximation Register Design Example......Page 478
 11.5 Sequential Multiplier Design......Page 490
 12.1 Subprograms......Page 502
 12.2 Functions......Page 506
 12.3 Procedures......Page 513
 12.4 Array Attributes and Unconstrained Arrays......Page 517
 12.5 Overloading Subprograms and Operators......Page 524
 12.6 Type Conversions......Page 527
 13.1 Packages and Package Bodies......Page 534
 13.2 Standard and De Facto Standard Packages......Page 538
 13.3 Package STD_LOGIC_1164......Page 543
 13.4 Package NUMERIC_STD (IEEE Std 1076.3)......Page 549
 13.5 Package STD_LOGIC_ARITH......Page 556
 13.6 Packages for VHDL Text Output......Page 557
 14.1 Simple Sequential Testbenches......Page 559
 14.2 Generating a System Clock......Page 560
 14.3 Generating the System Reset......Page 564
 14.4 Synchronizing Stimulus Generation and Monitoring......Page 565
 14.5 Testbench for Successive Approximation Register......Page 571
 14.6 Determining a Testbench Stimulus for a Sequential System......Page 575
 14.7 Using Procedures for Stimulus Generation......Page 578
 14.8 Output Verification in Stimulus Procedures......Page 583
 14.9 Bus Functional Models......Page 585
 14.10 Response Monitors......Page 593
 15.1 Modular Design, Partitioning, and Hierarchy......Page 599
 15.2 Design Units and Library Units......Page 604
 15.3 Design Libraries......Page 606
 15.4 Using Library Units......Page 607
 15.5 Direct Design Entity Instantiation......Page 610
 15.6 Components and Indirect Design Entity Instantiation......Page 613
 15.7 Configuration Declarations......Page 620
 15.8 Component Connections......Page 627
 15.9 Parameterized Design Entities......Page 631
 15.10 Library of Parameterized Modules (LPM)......Page 635
 15.11 Generate Statement......Page 638
 16.1 Microprocessor-Compatible QuadratureDecoder/Counter Design......Page 648
 16.2 Verification of Quadrature Decoder/Counter......Page 657
 16.3 Parameterized Quadrature Decoder/Counter......Page 661
 16.4 Electronic Safe Design......Page 663
 16.5 Verification of Electronic Safe......Page 677
 16.6 Encoder for RF Transmitter Design......Page 682
Appendix VHDL Attributes......Page 692
Bibliography......Page 696
Index......Page 698