Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog (Kluwer International Series in Engineering and Computer Science 667)

Verilog Quickstart: Practical Guide to Simulation & Synthesis in Verilog (3rd Ed.)......Page 1
Copyright......Page 5
Contents......Page 6
List of Figures......Page 14
List of Examples......Page 16
List of Tables......Page 22
Ch1 Introduction......Page 24
Design Abstraction Hierarchy......Page 26
Types of Languages......Page 27
HDL Learning Paradigms......Page 28
Where to Get More Information......Page 30
Usenet......Page 31
Identifiers......Page 32
Escaped Identifiers......Page 33
White Space......Page 34
Numbers......Page 35
Text Macros......Page 36
Semicolons......Page 37
Strengths......Page 38
Numbers, Values, and Unknowns......Page 39
Primitives......Page 42
Ports in Primitives......Page 43
Ports in Modules......Page 44
Hierarchy......Page 45
Hierarchical Names......Page 47
Connect by Name......Page 49
Top-Level Modules......Page 50
Exercise 2 The 8-Bit Hierarchical Adder......Page 51
Ch4 Starting Procedural Modeling......Page 56
The always Keyword......Page 57
Delays......Page 58
begin-end Blocks......Page 59
fork-join Blocks......Page 62
Summary of Procedural Timing......Page 69
$display and its Relatives......Page 70
Other Commands to Print Results......Page 72
Writing to Files......Page 74
Setting the Default Radix......Page 76
Special Characters......Page 77
The Current Simulation Time......Page 78
Suppressing Spaces in Your Output......Page 79
Periodic Printouts......Page 81
Exercise 3 Printing Out Results from Wires Buried in the Hierarchy......Page 82
Nets......Page 84
Ranges......Page 86
Ports......Page 87
Memories......Page 88
Integers and Reals......Page 89
Time and Realtime......Page 90
Events......Page 91
Multi-Dimensional Arrays......Page 92
Ports & Regs......Page 93
Ch7 Procedural Assignments......Page 96
Procedural Assignments, Ports & Regs......Page 100
Procedural Assignment for Sequential Logic......Page 101
Philosophy of Intra-assignment Delays for Sequential Assignments......Page 102
Conventions Moving Forward......Page 103
Binary Operators......Page 104
Unary Operators......Page 106
Reduction Operators......Page 107
Ternary Operator......Page 108
Equality Operators......Page 109
Concatenations......Page 112
Logical vs Bit-Wise Operators......Page 114
Operating that are Not Legal on Reals......Page 115
Combining Operators......Page 116
Signed Operations......Page 117
Signed Constants......Page 118
Continuous Assignment......Page 120
Event Control......Page 124
The always Block for Combinatorial Logic......Page 125
Event Control Explained......Page 126
Summary of Procedural Timing......Page 129
The if Statement......Page 132
The case Statement......Page 133
The forever Loop......Page 137
The repeat Loop......Page 138
The while Loop......Page 139
The for Loop......Page 140
Exercise 4 Using Expressions and case......Page 141
Tasks......Page 148
Automatic Tasks......Page 152
Common Uses for Tasks......Page 153
Functions......Page 155
Functions and Integers......Page 157
Automatic Functions......Page 158
Exercise 5 Functions and Continuous Assignments......Page 159
Using the Event Data Type......Page 160
Procedural Continuous Assignments......Page 162
Modeling with inout Ports......Page 167
The disable Statement......Page 169
When is a Simulation Done?......Page 172
Ch13 User-Defined Primitives......Page 174
Pessimistic Mux......Page 175
The Gritty Details......Page 176
Sequential UDPs......Page 177
The Final Details......Page 180
Exercise 6 Using UDPs......Page 181
Ch14 Parameterized Modules......Page 184
N-Bit Adder......Page 185
N by M Mux......Page 186
N by M RAM......Page 187
Parameter Passing by Order......Page 188
Parameter Passing by Named List......Page 189
Values of parameters in module instances......Page 190
State Machine Types......Page 192
State Machine Modeling Style......Page 194
State Encoding Methods......Page 202
Default Conditions......Page 204
Implicit State Machines......Page 205
Registered & Unregistered Outputs......Page 206
Factors in Choosing a State Machine Modeling Style......Page 208
Modeling Combinatorial Logic......Page 210
Combinatorial Models Using Continuous Assignments......Page 211
Combinatorial Models Using the always Block and regs......Page 212
Combinatorial Models Using Functions......Page 215
Sequential Models Using initial......Page 216
Sequential Models Using Tasks......Page 219
Modeling a One-Shot......Page 221
Modeling Asynchronous Systems......Page 222
Two-Dimensional Arrays......Page 228
Z-Detectors......Page 229
Multiplier Examples......Page 230
A Proven, Successful Approach to Modeling......Page 240
Forces that Influence Modeling Style......Page 242
Evolution of a Model......Page 243
Modeling Style and Synthesis......Page 244
Is It Synthesizable?......Page 245
Learning from Other People's Mistakes......Page 246
When to Uses UDPs......Page 253
Blocking and Non-Blocking Assignments......Page 254
Introduction to Testing......Page 256
Model Size vs Test Volume......Page 257
Sign-Off......Page 258
Creating Test Plans......Page 259
The Basic Test Cycle......Page 260
The Test Cycle for Combinatorial Models......Page 261
The Test Cycle for Sequential Models......Page 262
Self-Checking Test Benches......Page 264
Response-Driven Stimulus......Page 269
Test Benches for inouts......Page 272
Loading Files into Verilog Memories......Page 274
Using a Script to Run Test Cases......Page 277
Modeling BIST......Page 278
The Surrounding and Capture Method......Page 280
File Organization......Page 286
ANSI Style ports......Page 288
Including Test Cases......Page 289
Model Reuse......Page 292
Pre-defined Text Macros......Page 293
Mismatched Ports......Page 294
Missing Regs......Page 295
Missing Widths......Page 296
Improper Use of Procedural Continuous Assignments......Page 297
Zero-Delay always Loops......Page 298
Missing Initialization......Page 299
Timing Errors......Page 300
Zero-Delay Races......Page 301
Tool Specific Pragmas......Page 302
Overview of Functional Debugging......Page 304
"I am here."......Page 305
Values......Page 306
Using Waveforms......Page 307
Going Interactive......Page 309
The Prompts......Page 310
Special Keys in Interactive Mode......Page 312
Command History......Page 317
The Key File......Page 320
Traversing and Observing......Page 326
Back-Tracing Fan-In......Page 330
Using force and release......Page 331
Catching Probelms Later in a Simulation......Page 332
Isolating Differences in Models......Page 334
Summary of Debugging......Page 335
Ch22 Code Coverage......Page 338
Code Coverage and Test Plans......Page 339
Code Coverage and FIFOs......Page 342
Code Coverage and Modeling Style......Page 345
AND......Page 348
NAND......Page 349
NOR......Page 350
XNOR......Page 351
NOT......Page 352
BUFIF1......Page 353
NOTIF0......Page 354
PULLDOWN......Page 355
Switches......Page 356
NMOS and RNMOS......Page 357
PMOS and RPMOS......Page 358
CMOS and RCMOS......Page 359
TRANIF0 and RTRANIF0......Page 360
Delays......Page 361
Delay Units......Page 362
Strengths......Page 363
Displaying Strengths with %v......Page 364
Strength Reduction of Switch Primitives......Page 365
Index......Page 366