Verilog Hardware Description Language. IEEE 1364

CONTENTS......Page 4
Foreword......Page 21
IEEE Introduction......Page 25
1.2 Conventions used in this standard......Page 27
1.4 Contents of this standard......Page 28
1.5 Header file listings......Page 30
1.7 Prerequisites......Page 31
2.5 Numbers......Page 32
2.6 Strings......Page 36
2.7 Identifiers, keywords, and system names......Page 38
2.8 Attributes......Page 40
3.2 Nets and variables......Page 46
3.3 Vectors......Page 49
3.4 Strengths......Page 50
3.7 Net types......Page 51
3.9 Integers, reals, times, and realtimes......Page 57
3.10 Arrays......Page 59
3.11 Parameters......Page 60
3.12 Name spaces......Page 64
4.1 Operators......Page 66
4.2 Operands......Page 78
4.3 Minimum, typical, and maximum delay expressions......Page 83
4.4 Expression bit lengths......Page 85
4.5 Signed expressions......Page 88
5.3 The stratified event queue......Page 90
5.4 The Verilog simulation reference model......Page 91
5.6 Scheduling implication of assignments......Page 92
6.1 Continuous assignments......Page 95
6.2 Procedural assignments......Page 99
7.1 Gate and switch declaration syntax......Page 101
7.2 and, nand, nor, or, xor, and xnor gates......Page 107
7.3 buf and not gates......Page 108
7.4 bufif1, bufif0, notif1, and notif0 gates......Page 109
7.5 MOS switches......Page 110
7.7 CMOS switches......Page 112
7.8 pullup and pulldown sources......Page 113
7.9 Logic strength modeling......Page 114
7.10 Strengths and values of combined signals......Page 115
7.13 Strengths of net types......Page 128
7.14 Gate and net delays......Page 129
8.1 UDP definition......Page 133
8.2 Combinational UDPs......Page 137
8.4 Edge-sensitive sequential UDPs......Page 138
8.5 Sequential UDP initialization......Page 139
8.6 UDP instances......Page 141
8.7 Mixing level-sensitive and edge-sensitive descriptions......Page 142
8.8 Level-sensitive dominance......Page 143
9.1 Behavioral model overview......Page 144
9.2 Procedural assignments......Page 145
9.3 Procedural continuous assignments......Page 150
9.4 Conditional statement......Page 153
9.5 Case statement......Page 156
9.6 Looping statements......Page 160
9.7 Procedural timing controls......Page 162
9.8 Block statements......Page 172
9.9 Structured procedures......Page 175
10.2 Tasks and task enabling......Page 178
10.3 Functions and function calling......Page 183
11. Disabling of named blocks and tasks......Page 189
12.1 Modules......Page 192
12.2 Overriding module parameter values......Page 206
12.3 Ports......Page 211
12.4 Hierarchical names......Page 219
12.5 Upwards name referencing......Page 222
12.6 Scope rules......Page 224
13.1 Introduction......Page 226
13.2 Libraries......Page 227
13.3 Configurations......Page 229
13.4 Using libraries and configs......Page 233
13.5 Configuration examples......Page 234
13.7 Library mapping examples......Page 236
14.1 Specify block declaration......Page 238
14.2 Module path declarations......Page 239
14.3 Assigning delays to module paths......Page 249
14.4 Mixing module path delays and distributed delays......Page 253
14.5 Driving wired logic......Page 254
14.6 Detailed control of pulse filtering behavior......Page 255
15.1 Overview......Page 264
15.2 Timing checks using a stability window......Page 267
15.3 Timing checks for clock and control signals......Page 275
15.4 Edge-control specifiers......Page 285
15.5 Notifiers: user-defined responses to timing violations......Page 286
15.6 Enabling timing checks with conditioned events......Page 292
15.7 Vector signals in timing checks......Page 293
15.8 Negative timing checks......Page 294
16.2 Mapping of SDF constructs to Verilog......Page 296
16.3 Multiple annotations......Page 301
16.5 Pulse limit annotation......Page 302
16.6 SDF to Verilog delay value mapping......Page 303
17.1 Display system tasks......Page 304
17.2 File input-output system tasks and functions......Page 313
17.3 Timescale system tasks......Page 324
17.4 Simulation control system tasks......Page 328
17.5 PLA modeling system tasks......Page 329
17.6 Stochastic analysis tasks......Page 333
17.7 Simulation time system functions......Page 335
17.8 Conversion functions......Page 337
17.9 Probabilistic distribution functions......Page 338
17.10 Command line input......Page 347
18.1 Creating the four state value change dump file......Page 351
18.2 Format of the four state VCD file......Page 356
18.3 Creating the extended value change dump file......Page 366
18.4 Format of the extended VCD file......Page 370
19.2 `default_nettype......Page 377
19.3 `define and `undef......Page 378
19.4 `ifdef, `else, `elsif, `endif, `ifndef......Page 380
19.6 `resetall......Page 384
19.8 `timescale......Page 385
19.9 `unconnected_drive and `nounconnected_drive......Page 387
20.2 User-defined system task or function names......Page 388
20.6 PLI interface mechanism......Page 389
20.9 PLI Memory Restrictions......Page 390
21.1 User-supplied PLI applications......Page 391
21.2 Associating PLI applications to a class and system task/function name......Page 392
21.3 PLI application arguments......Page 393
22.2 The handle data type......Page 395
22.4 List of ACC routines by major category......Page 396
22.5 Accessible objects......Page 402
22.6 ACC routine types and fulltypes......Page 410
22.7 Error handling......Page 413
22.8 Reading and writing delay values......Page 415
22.9 String handling......Page 421
22.10 Using VCL ACC routines......Page 423
23. ACC routine definitions......Page 430
24.3 Reading and writing system task/function argument values......Page 605
24.6 Simulation synchronization......Page 607
24.11 Stopping and finishing......Page 608
25. TF routine definitions......Page 609
26.2 The VPI interface......Page 685
26.3 VPI object classifications......Page 687
26.4 List of VPI routines by functional category......Page 690
26.5 Key to data model diagrams......Page 692
27. VPI routine definitions......Page 726
Annex A (normative) Formal syntax definition......Page 787
Annex B (normative) List of keywords......Page 812
Annex C (informative) System tasks and functions......Page 814
Annex D (informative) Compiler directives......Page 821
Annex E (normative) acc_user.h......Page 823
Annex F (normative) veriuser.h......Page 832
Annex G (normative) vpi_user.h......Page 840
Annex H (informative) Bibliography......Page 854
Annex I (informative) List of  Participants......Page 855