Timing

Team LiB......Page 1
Cover......Page 2
Contents......Page 9
Acknowledgements......Page 13
1. PREDUCTION/INTROFACE......Page 15
2.1 Introduction......Page 19
2.2 Formulation of circuit equations......Page 20
2.3 Examples of equation formulation by inspection......Page 27
2.4 Solution of nonlinear equations......Page 28
2.5 Solution of differential equations......Page 32
2.6 Putting it all together......Page 38
2.7 A primer on solving systems of linear equations......Page 39
2.8 Summary......Page 45
3.1 Introduction......Page 47
3.2 Interconnect modeling......Page 50
3.3 Typical interconnect structures......Page 52
3.4 The Elmore delay metric......Page 54
3.5 Asymptotic waveform evaluation......Page 58
3.6 Krylov subspace-based methods......Page 69
3.7 Fast delay metrics......Page 77
3.8 Realizable circuit reduction......Page 82
3.9 Summary......Page 84
4.1 Introduction......Page 85
4.2 Identifying a logic stage......Page 86
4.3 Delay calculation under purely capacitive loads......Page 87
4.4 Effective capacitance: Delays under RC loads......Page 91
4.5 Capacitive coupling effects......Page 99
4.6 Summary......Page 110
5.2 Representation of combinational and sequential circuits......Page 111
5.3 False paths......Page 121
5.4 Finding the k most critical paths......Page 123
5.5 Summary......Page 125
6.1 Introduction......Page 127
6.2 Modeling parameter variations......Page 130
6.3 Early work on statistical STA......Page 135
6.4 Statistical STA in the absence of spatial correlation......Page 137
6.5 Statistical STA under spatial correlations......Page 140
6.6 Summary......Page 146
7.1 Introduction......Page 147
7.2 Clocking disciplines: Edge-triggered circuits......Page 149
7.3 Clocking disciplines: Level-clocked circuits......Page 151
7.4 Clock schedule optimization for level-clocked circuits......Page 158
7.5 Timing analysis of domino logic......Page 159
7.6 Summary......Page 163
8.1 Introduction......Page 165
8.2 Transistor sizing......Page 166
8.3 The TILOS algorithm......Page 171
8.4 Transistor sizing using convex programming......Page 175
8.5 Lagrangian multiplier approaches......Page 176
8.6 Timing budget based optimization......Page 180
8.7 Generalized posynomial delay models for transistor sizing......Page 181
8.8 Dual V[sub(t)] optimization......Page 189
8.9 Resolving short path violations......Page 191
8.10 Summary......Page 192
9.1 Accidental and deliberate clock skew......Page 195
9.2 Clock network construction......Page 197
9.3 Clock skew optimization......Page 204
9.4 Clock skew optimization with transistor sizing......Page 210
9.5 Timing analysis of sequential circuits for skew scheduling......Page 215
9.6 Wave pipelining issues......Page 217
9.7 Deliberate skews for peak current reduction......Page 218
9.8 Summary......Page 219
10.1 Introduction to retiming......Page 221
10.2 A broad overview of research on retiming......Page 225
10.3 Modeling and assumptions for retiming......Page 228
10.4 Minimum period optimization of edge-triggered circuits......Page 230
10.5 Minimum area retiming of edge-triggered circuits......Page 241
10.6 Minimum period retiming of level-clocked circuits......Page 254
10.8 Summary......Page 261
11. CONCLUSION......Page 263
A.1 Cubic equations......Page 265
A.2 Quartic equations......Page 266
B–A Gaussian approximation of the PDF of the maximum of two Gaussians......Page 267
C.1 Proof of convexity......Page 269
C.2 Relation of a generalized posynomial program to a posynomial program......Page 271
References......Page 273
D......Page 305
P......Page 306
T......Page 307
Z......Page 308