System on Package: Miniaturization of the Entire System

Contents......Page 11
Foreword......Page 19
Preface......Page 21
1 Introduction to the System-on-Package (SOP) Technology......Page 25
1.1 Introduction......Page 26
1.2 Electronic System Trend to Digital Convergence......Page 27
1.3 Building Blocks of an Electronic System......Page 29
1.4 System Technologies Evolution......Page 30
1.5.2 System-on-Chip (SOC) with Two or More System Functions on a Single Chip......Page 33
1.5.4 Stacked ICs and Packages (SIP): Package-Enabled IC Integration with Two or More Chip Stacking (Moore’s Law in the Third Dimension)......Page 35
1.6 System-on-Package Technology (Module with the Best of IC and System Integration)......Page 40
1.6.1 Miniaturization Trend......Page 44
1.7 Comparison of the Five System Technologies......Page 45
1.8.1 Opto SOP......Page 48
1.8.2 RF SOP......Page 50
1.9 SOP Technology Implementations......Page 51
1.10 SOP Technologies......Page 55
References......Page 56
2 Introduction to System-on-Chip (SOC)......Page 61
2.1 Introduction......Page 62
2.2 Key Customer Requirements......Page 64
2.3 SOC Architecture......Page 66
2.4.1 SOC Design Phase 1—SOC Definition and Challenges......Page 72
2.4.2 SOC Design Phase II—SOC Create Process and Challenges......Page 79
References......Page 98
3 Stacked ICs and Packages (SIP)......Page 103
3.1.3 CEO Figure and SIP Categories......Page 104
3.2.1 Materials and Process Challenges......Page 107
3.2.2 Mechanical Challenges......Page 109
3.2.3 Electrical Challenges......Page 110
3.2.4 Thermal Challenges......Page 111
3.3.1 Historical Evolution of Non-TSV SIP......Page 115
3.3.2 Chip Stacking......Page 118
3.3.3 Package Stacking......Page 135
3.3.4 Chip Stacking versus Package Stacking......Page 142
3.4.1 Introduction......Page 143
3.4.2 Historical Evolution of 3D TSV Technology......Page 146
3.4.3 Basic TSV Technologies......Page 148
3.4.4 Different 3D Integration Technologies using TSV......Page 156
3.4.5 Si Carrier Technology......Page 163
3.5 Future Trends......Page 165
References......Page 166
4 Mixed-Signal (SOP) Design......Page 173
4.1 Introduction......Page 174
4.1.1 Mixed-Signal Devices and Systems......Page 175
4.1.2 Importance of Integration in Mobile Applications......Page 177
4.1.3 Mixed-Signal Architecture......Page 178
4.1.4 Mixed-Signal Design Challenges......Page 179
4.1.5 Fabrication Technologies......Page 181
4.2 Design of Embedded Passives in RF Front End......Page 182
4.2.1 Embedded Inductors......Page 183
4.2.2 Embedded Capacitors......Page 188
4.2.3 Embedded Filters......Page 189
4.2.4 Embedded Baluns......Page 193
4.2.5 Filter-Balun Networks......Page 197
4.2.6 Tunable Filters......Page 200
4.3 Chip-Package Codesign......Page 202
4.3.1 Low Noise Amplifier Design......Page 203
4.3.2 Concurrent Oscillator Design......Page 206
4.4 Design of WLAN Front-End Module......Page 213
4.5 Design Tools......Page 216
4.5.1 Synthesis of Embedded RF Circuits......Page 217
4.5.2 Modeling of Signal and Power Delivery Networks......Page 220
4.5.3 Rational Functions, Network Synthesis, and Transient Simulation......Page 226
4.5.4 Design for Manufacturing......Page 230
4.6.1 Analog-to-Analog Coupling......Page 236
4.6.2 Digital-to-Analog Coupling......Page 244
4.7 Decoupling......Page 249
4.7.1 Need for Decoupling in Digital Applications......Page 250
4.7.2 Issues with SMD Capacitors......Page 251
4.7.3 Embedded Decoupling......Page 252
4.7.4 Characterization of Embedded Capacitors......Page 257
4.8 Electromagnetic Bandgap (EBG) Structures......Page 261
4.8.1 Analysis and Design of EBG Structures......Page 264
4.8.2 Application of EBGs in Power Supply Noise Suppression......Page 268
4.8.3 Radiation Analysis of EBGs......Page 270
4.9 Summary......Page 272
References......Page 273
5 Radio Frequency System-on-Package (RF SOP)......Page 283
5.2 RF SOP Concept......Page 284
5.3 Historical Evolution of RF Packaging Technologies......Page 287
5.4.1 Modeling and Optimization......Page 289
5.4.2 RF Substrate Materials Technologies......Page 290
5.4.3 Antennas......Page 291
5.4.4 Inductors......Page 300
5.4.5 RF Capacitors......Page 304
5.4.6 Resistors......Page 310
5.4.7 Filters......Page 317
5.4.8 Baluns......Page 319
5.4.9 Combiners......Page 320
5.4.10 RF MEMS Switches......Page 322
5.4.11 RFIDs......Page 327
5.5.1 WLAN......Page 330
5.5.2 Intelligent Network Communicator (INC)......Page 332
5.6 Future Trends......Page 334
Acknowledgments......Page 335
References......Page 336
6 Integrated Chip-to-Chip Optoelectronic SOP......Page 343
6.1 Introduction......Page 344
6.2.1 High-Speed Digital Systems and High-Performance Computing......Page 345
6.2.2 RF-Optical Communication Systems......Page 346
6.3 Integration Challenges in Thin-Film Optoelectronic SOP......Page 347
6.3.2 Key Physical and Optical Properties of Thin-Film Optical Waveguide Materials......Page 348
6.4.1 Comparison of High-Speed Electrical and Optical Wiring Performance......Page 353
6.4.2 Wiring Density......Page 354
6.4.3 Power Dissipation......Page 356
6.4.4 Reliability......Page 357
6.5.1 Board-to-Board Optical Wiring......Page 358
6.5.2 Chip-to-Chip Optical Interconnects......Page 361
6.6 Optoelectronic SOP Thin-Film Components......Page 363
6.6.1 Passive Thin-Film Lightwave Circuits......Page 364
6.6.2 Active Optoelectronic SOP Thin-Film Components......Page 376
6.6.3 Opportunities for 3D Lightwave Circuits......Page 377
6.7 SOP Integration: Interface Optical Coupling......Page 379
6.8 On-Chip Optical Circuits......Page 385
6.10 Summary......Page 387
References......Page 388
Table 6.1 References......Page 396
7 SOP Substrate with Multilayer Wiring and Thin-Film Embedded Components......Page 399
7.1 Introduction......Page 400
7.2 Historical Evolution of Substrate Integration Technologies......Page 402
7.3.1 Drivers and Challenges......Page 403
7.3.2 Ultrathin-Film Wiring with Embedded Low-K Dielectrics, Cores, and Conductors......Page 406
7.3.3 Embedded Passives......Page 437
7.3.4 Embedded Actives......Page 452
7.3.5 Miniaturized Thermal Materials and Structures......Page 456
7.4 Future SOP Substrate Integration......Page 457
References......Page 459
8 Mixed-Signal (SOP) Reliability......Page 465
8.1 System-Level Reliability Considerations......Page 467
8.1.1 Failure Mechanisms......Page 468
8.1.2 Design-for-Reliability......Page 469
8.1.3 Reliability Verification......Page 471
8.2.1 Materials and Process Reliability......Page 472
8.2.2 Digital Function Reliability and Verification......Page 480
8.2.3 RF Function Reliability and Verification......Page 483
8.2.4 Optical Function Reliability and Verification......Page 485
8.2.5 Multifunction System Reliability......Page 489
8.3 Substrate-to-IC Interconnection Reliability......Page 490
8.3.1 Factors Affecting the Substrate-to-IC Interconnection Reliability......Page 491
8.3.2 100-μm Flip-Chip Assembly Reliability......Page 493
8.3.4 Solder Joint Reliability......Page 498
8.3.5 Interfacial Adhesion and Effect of Moisture on Underfill Reliability......Page 500
8.4 Future Trends and Directions......Page 504
8.4.1 Extending Solder......Page 505
8.4.3 Alternative to Solder and Nano Interconnects......Page 506
8.5 Summary......Page 508
References......Page 509
9 MEMS Packaging......Page 517
9.2 Challenges in MEMS Packaging......Page 518
9.3 Chip-Scale versus Wafer-Scale Packaging......Page 519
9.4 Wafer Bonding Techniques......Page 521
9.4.2 Bonding Using Intermediate Layers......Page 522
9.5.1 Etching the Sacrificial Material......Page 527
9.5.2 Decomposition of Sacrificial Polymers......Page 531
9.6 Low-Loss Polymer Encapsulation Techniques......Page 536
9.7.1 Nonevaporable Getters......Page 538
9.7.2 Thin-Film Getters......Page 539
9.7.3 Improving MEMS Reliability through Getters......Page 542
9.8 Interconnections......Page 544
9.9 Assembly......Page 546
9.10 Summary and Future Trends......Page 549
References......Page 550
10 Wafer-Level SOP......Page 557
10.1.1 Definition......Page 558
10.1.2 Wafer-Level Packaging—Historical Evolution......Page 559
10.2.1 IC-Package Pitch Gap......Page 562
10.2.2 Redistribution Layers on Si to Close the Pitch Gap......Page 565
10.3.1 Embedded Thin-Film Components in the ReDistribution Layer (RDL)......Page 566
10.4 Wafer-Level Packaging and Interconnections (WLPI)......Page 570
10.4.1 Classes of Wafer-Level Packaging and Interconnections (WLPI)......Page 574
10.4.2 Rigid Interconnections......Page 582
10.4.3 WLSOP Assembly......Page 607
10.4.4 WLSOP......Page 612
10.5 Wafer-Level Probing and Burn-In......Page 613
References......Page 617
11 Thermal SOP......Page 627
11.1 Fundamentals of Thermal SOP......Page 628
11.1.1 Thermal Implications of SOP......Page 629
11.1.2 System-Level Thermal Constraints in SOP-Based Portables......Page 631
11.2 Thermal Sources in SOP Modules......Page 632
11.2.1 Digital SOP......Page 633
11.2.2 RF SOP......Page 635
11.2.3 Optoelectronic SOP......Page 637
11.2.4 MEMS SOP......Page 639
11.3.1 Conduction......Page 640
11.3.2 Convection......Page 645
11.3.3 Radiation......Page 648
11.4.1 Numerical Methods for Thermal Characterization......Page 651
11.5 Thermal Management Technologies......Page 659
11.5.1 Thermal Design Methodologies......Page 660
11.6 Power Minimization Methodologies......Page 670
11.6.2 Dynamic Voltage and Frequency Scaling (DVFS)......Page 671
11.6.4 Cache Power Minimization......Page 672
Acknowledgment......Page 673
References......Page 674
12 Electrical Test of SOP Modules and Systems......Page 681
12.1 SOP Electrical Test Challenges......Page 682
12.1.1 Objectives of the HVM Test Process and Challenges for SOPs......Page 684
12.1.2 HVM Test Flow for SOPs......Page 685
12.2.1 Substrate Interconnect Tests......Page 686
12.2.2 Testing Embedded Passives......Page 693
12.3.1 Boundary Scan—IEEE 1149.1......Page 699
12.3.2 Multi-gigahertz Digital Test: Recent Developments......Page 703
12.4.1 Test Strategies......Page 707
12.4.2 Fault Models and Test Quality......Page 710
12.4.3 Direct Measurement of Specifications Using Dedicated Circuitry......Page 711
12.4.4 Alternate Testing Methods for Mixed-Signal and RF Circuits......Page 712
References......Page 729
13.1.1 SOP: A Highly Miniaturized Electronic System Technology......Page 739
13.1.2 Biosensor SOP for Miniaturized Biomedical Implants and Sensor Systems......Page 740
13.2.1 Microchannels for Biofluid Transport......Page 745
13.2.2 Biosensing Element (Probe) Design and Preparation......Page 746
13.2.3 Probe-Target Molecular Hybridization......Page 749
13.3.1 Nanomaterials and Nanostructures for Signal Conversion Components......Page 752
13.3.2 Surface Modification and Biofunctionalization of Signal Conversion Component......Page 756
13.3.3 Signal Conversion Methods......Page 757
13.4.1 Low-Power Application-Specific Integrated Circuits (ASICs) and Mixed-Signal Design for Biosensor SOP......Page 763
13.4.2 Bio- SOP Substrate Integration Technologies......Page 766
13.5.1 Nano Bio-SOP Integration Challenges......Page 767
References......Page 768
Index......Page 771
A......Page 773
B......Page 774
C......Page 776
D......Page 778
E......Page 780
F......Page 782
H......Page 784
I......Page 785
J......Page 786
L......Page 787
M......Page 788
N......Page 791
O......Page 792
P......Page 793
R......Page 796
S......Page 798
T......Page 802
V......Page 805
W......Page 806
Z......Page 807