System-on-Chip: Next Generation Electronics (Circuits, Devices and Systems)

Contents......Page 12
PART I – System-level design......Page 30
1 Multi-criteria decision making in embedded system design......Page 32
2 System-level performance analysis – the SymTA/S approach......Page 34
3 Analysis and optimisation of heterogeneous real-time embedded systems......Page 104
4 Hardware/software partitioning of operating systems: focus on deadlock avoidance......Page 150
Models of computation in the design process......Page 190
6 Architecture description languages for programmable embedded systems......Page 216
PART II –Embedded software......Page 250
7 Concurrent models of computation for embedded software......Page 252
8 Retargetable compilers and architecture exploration for embedded processors......Page 280
9 Software power optimisation......Page 318
PART III –Power reduction and management......Page 346
10 Power-efficient data management for dynamic applications......Page 348
11 Low power system scheduling, synthesis and displays......Page 390
12 Power minimisation techniques at the RT-level and below......Page 416
13 Leakage power analysis and reduction for nano-scale circuits......Page 444
PART IV – Reconfigurable computing......Page 478
14 Reconfigurable computing: architectures and design methods......Page 480
PART V–Architectural synthesis......Page 524
15 CAD tools for embedded analogue circuits in mixed-signal integrated Systems-on-Chip......Page 526
16 Clock-less circuits and system synthesis......Page 570
PART VI – Network-on-chip......Page 616
17 Network-on-chip architectures and design methods......Page 618
18 Asynchronous on-chip networks......Page 654
PART VII –Simulation and verification......Page 686
19 Covalidation of complex hardware/software systems......Page 688
20 Hardware/software cosimulation from interface perspective......Page 718
21 System-level validation using formal techniques......Page 744
PART VIII – Manufacturing test......Page 778
22 Efficient modular testing and test resource partitioning for core-based SoCs......Page 780
23 On-chip test infrastructure design for optimal multi-site testing......Page 820
24 High-resolution flash time-to-digital conversion and calibration for system-on-chip testing......Page 850
25 Yield and reliability prediction forDSM circuits......Page 886
Index......Page 920