System-on-Chip for Real-Time Applications

Front Matter....Pages i-xv
Front Matter....Pages 1-2
System on Chip....Pages 3-16
Electronic Product Innovation Using Direct Mapped Signal Processing SoC Cores....Pages 17-25
System-on-Chip Implementation of Signal Processors....Pages 26-28
Front Matter....Pages 29-30
Methodologies and Strategies for Effective Design-Reuse....Pages 31-40
A VHDL/SystemC Comparison in Handling Design Reuse....Pages 41-50
Aspect partitioning for Hardware Verification Reuse....Pages 51-60
Reconfigurable Combinatorial Accelerators for Real Time Processing....Pages 61-70
Tuning Methodologies for Parameterized Systems Design....Pages 71-82
Front Matter....Pages 83-84
Formal Verifications of Systems on Chips: Current and Future Directions ....Pages 85-97
A Practical Approach to the Formal Verification of SoC’s with Symbolic Model-Checking....Pages 98-110
High Performance Verification Solutions for SOC Designs....Pages 111-124
Novel Test Methodologies for SoC/IP Design....Pages 125-135
Front Matter....Pages 137-138
SOC Modeling and Simulation Based on Java....Pages 139-149
RTOS Modeling Using SystemC....Pages 150-159
Modeling, Synthesis and Implementation of Communicating Hierarchical FSM....Pages 160-169
A Modeling Method for Reconfigurable Architectures....Pages 170-179
Front Matter....Pages 181-182
The Syslib-Picasso Methodology for the Co-Design Specification Capture Phase....Pages 183-192
Automatic Porting of Binary File Descriptor Library....Pages 193-202
Code Compression on Transport Triggered Architectures....Pages 203-213
An Approach to Flexible Multi-Level Network Design....Pages 214-223
Front Matter....Pages 225-226
Survey of Emerging Nonvolatile Embedded Memory Technologies....Pages 227-236
Configurable Parallel Memory Implementation For System-on-Chip Designs....Pages 237-248
XOR-scheme Implementations In Configurable Parallel Memory....Pages 249-261
An Novel Low Power Embedded Memory Architecture for MPEG-4 Applications with Mobile Devices....Pages 262-272
Assessment of MPEG-4 VTC and JPEG2000 Dynamic Memory Requirements....Pages 273-283
Front Matter....Pages 285-286
Modified Distributed Arithmetic Architecture for Adiabatic DSP Systems....Pages 287-295
Design of a CMOS Wide Range Logarithmic Amplifier with a Modified Parallel Architecture....Pages 296-304
Digital Hardware Implementation OF Continuous And Discrete Chaotic Generators....Pages 305-313
Novel 1-bit Full Adder Cells for Low-Power System-On-Chip Applications....Pages 314-323
Front Matter....Pages 325-326
A New Logic Design Method for Considering Low Power and High Testability....Pages 327-338
System Synthesis for Optically-Connected, Multiprocessors On-Chip....Pages 339-348
Low Power System-on-Chip Platform Architecture for High Performance Applications....Pages 349-356
Front Matter....Pages 357-358
SoC Interconnect in Deep Submicron....Pages 359-379
Optimizing Inductive Interconnect for Low Power....Pages 380-391
Skin Effects in System on a Chip Interconnects....Pages 392-402
Front Matter....Pages 403-404
Road Map Towards Designing MEMS Devices With High-Reliability....Pages 405-410
A Mems Socket Interface For Soc Connectivity....Pages 411-420
On the Application of Finite Element to Investigate the Reliability of Electrostatic Comb-Drive Actuators Utilized in Microfluidic and Space systems....Pages 422-428
An HDL Model for A Vacuum -Sealed Micromachined Pressure Sensor....Pages 429-439
Performance Analysis of MEMS-based Inertial Sensors for Positioning Applications....Pages 440-450
Back Matter....Pages 451-456