State Machines using VHDL: FPGA Implementation of Serial Communication and Display Protocols

Preface
Acknowledgments
Abbreviations
Contents
1: State Machines and Modeling of Mathematical and Physical Problems by State Machines
	1.1	 State
		1.1.1	 State Diagrams and Mealy and Moore Models
			1.1.1.1	 Mealy and Moore Machines
		1.1.2	 State Names
		1.1.3	 State Machine Inputs and Outputs
	1.2	 Modeling of Mathematical and Real-Life Problems by State Machines
		1.2.1	 Some Applications of Finite State Machines
		1.2.2	 Mealy or Moore
	1.3	 Conversion Between Mealy and Moore State Diagrams/Machines
		1.3.1	 Conversion from Mealy to Moore State Diagrams/Machines
		1.3.2	 Conversion from Moore to Mealy State Machines
	1.4	 Modeling the Behavior of Electronic Circuits Using State Machines
		1.4.1	 Flip-Flops, Characteristic, and Excitation Tables
		1.4.2	 State Tables and State Diagrams of Sequential Circuits
	Problems
2: VHDL Implementation of Finite State Machines and Practical Applications
	2.1	 Implementation of Finite State Machines in VHDL
		2.1.1	 VHDL Implementation of Moore State Machines
		2.1.2	 VHDL Implementation of Mealy State Machines
	2.2	 Examples for VHDL Implementations of State Machines
		2.2.1	 Three-Bit Binary Counter in VHDL
		2.2.2	 Counter State Machine Program Flow Analysis
		2.2.3	 Predefined Encoding Types
		2.2.4	 Mealy State Diagram Implementation Example
		2.2.5	 Parity Generator Implementation Example
		2.2.6	 Non-overlapping Sequence Detector Implementation Example
		2.2.7	 Arbiter Implementation Example
		2.2.8	 VHDL Implementation of RS232 Asynchronous Serial Communication Protocol
			2.2.8.1	 VHDL Implementation of RS232 Transmitter
			2.2.8.2	 VHDL Implementation of RS232 Receiver
			2.2.8.3	 VHDL Implementation of RS232 Transceiver
		2.2.9	 VHDL Implementation of FIFO
		2.2.10	 VHDL Implementation of Buffered RS232 Receiver
	Problems
3: Timed Finite State Machines in VHDL
	3.1	 Timed State Machine Models
	3.2	 VHDL Implementation of Timed Moore State Machines
		3.2.1	 Timed Moore State Machine VHDL Implementation Example
	3.3	 Analysis of the Timed Moore State Machine
	3.4	 Seven-Segment Display as a Timed State Machine
	3.5	 The Implementation of Timed Mealy State Machines in VHDL
		3.5.1	 Example for the VHDL Implementation of Timed Mealy State Machine
	3.6	 Digital Transmitter Implementation Using Timed State Machines
	Problems
4: Serial Peripheral Interface
	4.1	 Synchronous Communication
	4.2	 Serial Peripheral Interface (SPI) Communication
		4.2.1	 MOSI and MISO Bit Transmission
			4.2.1.1	 The Steps of SPI Data Transmission
			4.2.1.2	 Properties of SPI Communication
		4.2.2	 SPI Operation Modes
			4.2.2.1	 Clock Polarity (CPOL)
			4.2.2.2	 Clock Phase
			4.2.2.3	 Summary
	4.3	 VHDL Implementation of SPI Communication
		4.3.1	 Implementation of SPI Protocols Only in Transmit Mode
			4.3.1.1	 Second Solution
		4.3.2	 Implementation of SPI Protocols Both in Transmit and Receive Mode
	4.4	 SPI VHDL Implementation Examples for Electronic Devices
		4.4.1	 VHDL Implementation of SPI Protocol for 12-bit DAC MCP4921
		4.4.2	 Sine Signal Generation and SPI Protocol Development in VHDL for Digital Analog Converter (DAC), AD7303
			4.4.2.1	 8-Bit Digital-to-Analog Converter, AD7303
			4.4.2.2	 Sine Signal Generation in VHDL
			4.4.2.3	 Second Solution
		4.4.3	 SPI Protocol Development in VHDL for Digital Output MEMS Accelerometer, ADXL362
			4.4.3.1	 SPI Protocol of ADXL362
	Problems
5: Inter Integrated Circuit (I2C) Serial Communication in VHDL
	5.1	 Master-Slave Connections and I2C Port Circuit
	5.2	 START, STOP, and IDLE Control Signals of I2C Protocol
	5.3	 Generation of Shifted Clock and Determination of the Transmission Instants
	5.4	 I2C Read and Write Operations
		5.4.1	 I2C Write Operation
		5.4.2	 I2C Read Operation
	5.5	 Data Transfer Formats
		5.5.1	 Write Operation
		5.5.2	 Master Reads the Slave Immediately
		5.5.3	 Combined Format Involving Repeated START
	5.6	 VHDL Implementation of I2C Protocol
	5.7	 VHDL Implementation of FPGA and ADT7420 I2C Interfacing
		5.7.1	 VHDL Implementation of I2C Communication Between FPGA and ADT7420
			5.7.1.1	 ID Register of ADT7420
			5.7.1.2	 VHDL Implementation
	Problems
6: Video Graphic Array (VGA) and HDMI Interfacing
	6.1	 Video Graphic Array (VGA)
		6.1.1	 Graphic Controller
		6.1.2	 VGA Monitors
		6.1.3	 Pixel Clock
	6.2	 Basic VGA Format
		6.2.1	 Hsync Signal
		6.2.2	 Vsync Signal
		6.2.3	 VGA Resolution Modes
	6.3	 VGA Connector
	6.4	 VHDL Design for VGA Interface
	6.5	 VHDL Implementation Examples
		6.5.1	 Generation and Display of Letter “I”
		6.5.2	 Generation and Display of Square Shape
		6.5.3	 Generation and Display of Moving Square
		6.5.4	 Generation and Display of a Filled-Circle and a Ring
		6.5.5	 Generation and Display of Radar Screen
	6.6	 High-Definition Multimedia Interfacing (HDMI) and VHDL Implementation of HDMI
		6.6.1	 TDMS Communication Channel
		6.6.2	 8b/10b Encoder
		6.6.3	 Implementation of TMDS Encoder in VHDL
		6.6.4	 Serializer in TMDS Communication Channel and Its VHDL Implementation
		6.6.5	 VHDL Implementation of HDMI
	Problems
Bibliography
Index