Split Manufacturing of Integrated Circuits for Hardware Security and Trust

Preface
Acknowledgments
Contents
About the Authors
Acronyms
List of Figures
List of Tables
1 Split Manufacturing Methods
	1.1 Integrated Circuit Design Process
	1.2 Integrated Circuit Fabrication
	1.3 Globalization of the IC Supply Chains
	1.4 Vulnerabilities in the IC Supply Chains
	1.5 Split Manufacturing of Integrated Circuits
	1.6 Security Benefits of SM
	1.7 SoC Design Methodology for SM
	1.8 Where to Split? Which Wires to Lift?
	1.9 Hardware Demonstrations of Secure SM
	1.10 SM for 2.5D Integrated Circuits
	1.11 SM for 3D Integrated Circuits
	1.12 Attacks Against SM
		1.12.1 Attacker's Location
		1.12.2 Attacker's Objective
		1.12.3 Attack Methodology
		1.12.4 Validation of the Recovered Design
		1.12.5 Benchmarks
	1.13 Summary
	References
2 Design Constraint Based Attacks
	2.1 General Approach
	2.2 Attack Evaluation Metrics
	2.3 Proximity Attack
		2.3.1 Attack Assumptions
		2.3.2 Attack Algorithm
		2.3.3 Discussion
	2.4 Extended Proximities
		2.4.1 Types of Proximity
		2.4.2 Discussion
	2.5 Network Flow Attack
		2.5.1 Attack Assumptions
		2.5.2 Attack Algorithm
		2.5.3 Discussion
	2.6 Machine Learning Attack
		2.6.1 Classifier Development
		2.6.2 Further Enhancements
		2.6.3 Discussion
	2.7 Simulated Annealing (SA) Based Trojan Insertion Attack
		2.7.1 Mapping Problem Formulation
		2.7.2 SA Based Mapping
		2.7.3 Evaluation Metrics
		2.7.4 Discussion
	2.8 Proximity Based Mapping and Net Based Pruning
		2.8.1 Proximity Based Mapping
		2.8.2 Net Based Pruning
		2.8.3 Discussion
	2.9 Structural Pattern Matching Attack
		2.9.1 Pattern Tables
		2.9.2 Pattern Matching
		2.9.3 Discussion
	2.10 Summary
	References
3 Defenses Against Design Constraint Based Attacks
	3.1 Defense Metrics
	3.2 General Defense Methods
	3.3 Defense Cost
	3.4 Pin Swapping
		3.4.1 Objective
		3.4.2 Algorithm
		3.4.3 Discussion
	3.5 Secure Min-Cut Bipartitioning and Placement
		3.5.1 Objective
		3.5.2 Algorithm
		3.5.3 Discussion
	3.6 Secure Multiway Min-Cut Partitioning
		3.6.1 Objective
		3.6.2 Secure Partitioning
		3.6.3 Global Placement for Minimum Wire Length
		3.6.4 Discussion
	3.7 Placement Perturbation
		3.7.1 Objective
		3.7.2 Gate Selection
		3.7.3 Placement Perturbation
		3.7.4 Discussion
	3.8 Routing Perturbation
		3.8.1 Objective
		3.8.2 Algorithm
		3.8.3 Discussion
	3.9 Concerted Wire Lifting
		3.9.1 Objective
		3.9.2 Algorithm
		3.9.3 Discussion
	3.10 Netlist Clustering
		3.10.1 Gate Type Based Clustering
		3.10.2 Graph Coloring Based Clustering
		3.10.3 Discussion
	3.11 Artificial Routing Blockage Insertion
		3.11.1 Branch Insertion
		3.11.2 Blockage Insertion
		3.11.3 Discussion
	3.12 Netlist Randomization
		3.12.1 Objective
		3.12.2 Algorithm
		3.12.3 Discussion
	3.13 Summary
	References
4 Satisfiability Based Attacks
	4.1 Background
		4.1.1 Satisfiability Checking
		4.1.2 Logic Encryption
		4.1.3 Satisfiability (SAT) Attack Against Logic Encryption
		4.1.4 Cyclic Logic Locking and CycSAT Attack
	4.2 Satisfiability Based Layout Recognition
	4.3 SAT Attack Based Reverse Engineering
		4.3.1 Modeling BEOL Recovery as Logic Decryption
		4.3.2 Elimination of Cyclic Paths
		4.3.3 Attack Algorithm
		4.3.4 Discussion
	4.4 SAT Attack Against Split Sequential Circuits
		4.4.1 Attack Methodology
		4.4.2 Discussion
	4.5 SAT Attacks Including Proximity Information
		4.5.1 Proximity Information
		4.5.2 Reduction of Key-Controlled Network
		4.5.3 Attack Algorithm for Combinational Circuits
		4.5.4 Attack Algorithm for Sequential Circuits
		4.5.5 Discussion
	4.6 SMT Based Reduction of Key Network Complexity
		4.6.1 Hard Grouping Hints
		4.6.2 Algorithm for Hard Grouping
		4.6.3 Soft Grouping Hints
		4.6.4 Discussion
	4.7 Summary
	References
5 Defenses Against Satisfiability Based Attacks
	5.1 SAT Based Greedy Wire Lifting
		5.1.1 Objective
		5.1.2 Algorithm
		5.1.3 Discussion
	5.2 Simultaneous Wire Lifting and Cell Insertion
		5.2.1 Objective
		5.2.2 Secure Implementations
		5.2.3 Netlist Manipulation Algorithm
		5.2.4 Secure Layout
		5.2.5 Discussion
	5.3 Combined Layout Camouflaging and SM
		5.3.1 Objective
		5.3.2 Tool Flow
		5.3.3 Discussion
	5.4 Combined Logic Encryption and SM
		5.4.1 Methodology and Tool Flow
		5.4.2 Discussion
	5.5 Combined Layout Camouflaging and SM for 3D ICs
		5.5.1 Design Methodology for IP Protection
		5.5.2 Discussion
		5.5.3 Design Methodology for Trojan Prevention
		5.5.4 Discussion
	5.6 Obfuscated Built-In Self-Authentication
		5.6.1 OBISA Obfuscated Connection Approach
		5.6.2 OBISA Wire Lifting Approach
		5.6.3 Discussion
	5.7 Summary
	References
6 Challenges and Research Directions
	6.1 Challenges
	6.2 Splitting at Higher Levels of Abstraction
	6.3 SM for Analog and Mixed-Signal Designs
	6.4 SM with Novel Devices
	6.5 Novel Attacks Against SM
	6.6 SM Manufacturability vs. Security
	6.7 Advances in Machine Learning for SM
	6.8 Summary
	References
A Benchmarks
	References
Index