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ویرایش:
نویسندگان: Sonia Belaïd (editor). Tim Güneysu (editor)
سری:
ISBN (شابک) : 3030420671, 9783030420673
ناشر: Springer
سال نشر: 2020
تعداد صفحات: 280
[270]
زبان: English
فرمت فایل : PDF (درصورت درخواست کاربر به PDF، EPUB یا AZW3 تبدیل می شود)
حجم فایل: 22 Mb
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در صورت تبدیل فایل کتاب Smart Card Research and Advanced Applications: 18th International Conference, CARDIS 2019, Prague, Czech Republic, November 11–13, 2019, Revised Selected Papers (Security and Cryptology) به فرمت های PDF، EPUB، AZW3، MOBI و یا DJVU می توانید به پشتیبان اطلاع دهید تا فایل مورد نظر را تبدیل نمایند.
توجه داشته باشید کتاب تحقیقات کارت هوشمند و کاربردهای پیشرفته: هجدهمین کنفرانس بین المللی، CARDIS 2019، پراگ، جمهوری چک، 11 تا 13 نوامبر 2019، مقالات منتخب اصلاح شده (امنیت و رمز شناسی) نسخه زبان اصلی می باشد و کتاب ترجمه شده به فارسی نمی باشد. وبسایت اینترنشنال لایبرری ارائه دهنده کتاب های زبان اصلی می باشد و هیچ گونه کتاب ترجمه شده یا نوشته شده به فارسی را ارائه نمی دهد.
این کتاب مجموعه مقالات پس از کنفرانس هجدهمین کنفرانس بین المللی تحقیقات و کاربردهای پیشرفته کارت هوشمند، CARDIS 2019، که در پراگ، جمهوری چک، در نوامبر 2019 برگزار شد، تشکیل شده است. 15 مقاله کامل اصلاح شده ارائه شده در این کتاب به دقت بررسی شده و از بین 31 ارسال انتخاب شده است. مقالات در بخش های موضوعی زیر سازماندهی شده اند: امنیت سیستم روی یک تراشه. رمزنگاری پس کوانتومی؛ تجزیه و تحلیل کانال جانبی؛ حملات ریزمعماری؛ رمزنگاری اولیه؛ پیشرفت در تحلیل کانال جانبی CARDIS فضایی را برای کارشناسان امنیتی از صنعت و دانشگاه فراهم کرده است تا در مورد امنیت کارت های هوشمند و برنامه های کاربردی مربوطه تبادل نظر کنند.
This book constitutes the thoroughly refereed post-conference proceedings of the 18th International Conference on Smart Card Research and Advanced Applications, CARDIS 2019, held in Prague, Czech Republic, in November 2019. The 15 revised full papers presented in this book were carefully reviewed and selected from 31 submissions. The papers are organized in the following topical sections: system-on-a-chip security; post-quantum cryptography; side-channel analysis; microarchitectural attacks; cryptographic primitives; advances in side-channel analysis. CARDIS has provided a space for security experts from industry and academia to exchange on security of smart cards and related applications.
Preface Organization Contents System-on-a-Chip Security In-situ Extraction of Randomness from Computer Architecture Through Hardware Performance Counters 1 Introduction 2 Preliminaries on Hardware Performance Counters 3 Non-determinism of HPCs and Motivation 4 Randomness Extraction Using HPCs 4.1 Selection of the Least Significant Bits 4.2 Selection of HPC Events Using Yao's Next-Bit Test 5 Experimental Validation 5.1 Results on TRNG Output Obtained from HPC Events 5.2 Perturbation in TRNG Output in Presence of an Adversary 6 Hybrid Construction to Enhance Throughput 6.1 Cryptographic Post-processing of the TRNG Output 6.2 Results on TRNG Output Obtained from Hybrid Construction 7 Discussion 8 Conclusion References Optimized Threshold Implementations: Minimizing the Latency of Secure Cryptographic Accelerators 1 Introduction 2 Preliminaries 2.1 Threshold Implementations 2.2 Minimizing Implementation Overheads Using S-box Decomposition 2.3 A Note on Latency and Energy Efficiency 3 Finding an Efficient Sharing 4 Hardware Implementation 4.1 Synthesis Results and Side-Channel Evaluation 5 Conclusion and Outlook References Breaking the Lightweight Secure PUF: Understanding the Relation of Input Transformations and Machine Learning Resistance 1 Introduction 1.1 Main Contribution 2 Background 2.1 Machine Learning Attacks on PUFs 2.2 Notation 2.3 Modeling XOR Arbiter PUFs 3 Input Transformations: Classic vs. Random 3.1 Pseudorandom Input Transformation 3.2 Local Minima 4 Input Transformations: Lightweight Secure 4.1 Feature Vector Correlation 4.2 Improved Attack 5 Solution 5.1 Permutation-Based Input Transformations 6 Conclusion References Post-Quantum Cryptography Improving Speed of Dilithium's Signing Procedure 1 Introduction 2 Preliminaries 2.1 Dilithium 3 Early Evaluation Optimization 3.1 Note on Timing Attacks 3.2 Additional Optimizations 4 Experimental Results 4.1 A Refined Evaluation Approach 4.2 Results on the Intel Core i5-4460 CPU 4.3 Results on the ARM Cortex-M4 4.4 Memory Requirements for Scenario-2 and Scenario-3 5 Conclusion References An Efficient and Provable Masked Implementation of qTESLA 1 Introduction 2 Preliminaries 2.1 Notations 2.2 Masking 2.3 The qTESLA Signature 3 Masked qTESLA 3.1 Masking-Friendly Design 3.2 Existing Gadgets 3.3 New Gadgets 3.4 Masked Scheme 4 Proof of Masking 4.1 Main Masking Theorem 4.2 EUF-CMA Security in the N-probing Model 5 Practical Aspects References Side-Channel Analysis Side-Channel Attacks on Blinded Scalar Multiplications Revisited 1 Introduction 1.1 Preliminaries and Notations 1.2 Overall Attack Process 1.3 Paper Organization and Contributions 2 Previous Works 2.1 A Divide and Conquer Algorithm 2.2 Schindler and Wiemers' Phase 1 Algorithm 2.3 Empirical Improvements 2.4 Some Results 3 Improved Algorithms 3.1 First Observations 3.2 Keeping a List of the Blinding Factors Best Candidates 3.3 Algorithms Improvements in Detail 3.4 Simulation Results and Comparisons 4 Conclusion and Future Work References Remote Side-Channel Attacks on Heterogeneous SoC 1 Introduction 2 Background 2.1 Power Side-Channel Attacks 2.2 FPGA-Based Voltage Sensors 2.3 Threat Model 2.4 Related Works 3 Presentation of the Side-Channel Setup 3.1 Side-Channel Sensors 3.2 Side-Channel Targets 3.3 Xilinx Zynq Experimental Setup 4 FPGA-Based Attack on Hardware AES 5 FPGA-Based Attack on Software AES 5.1 Experiment 1: 8-Bit Tiny AES 5.2 Experiment 2: 32-Bit OpenSSL AES 6 EM Results and Discussion 6.1 Electromagnetic Side-Channel Attack 6.2 Attack Feasibility 6.3 Countermeasures 7 Conclusion 8 Appendix References Optimal Collision Side-Channel Attacks 1 Introduction 2 Background and Model Notations 2.1 Collision Side-Channel Attacks 2.2 Stochastic and Correlation Enhanced Collision Attacks 3 Optimal Distinguishers for Random Leakage Functions 4 Optimal Evaluation of Distinguishers 4.1 Random Space Exploration 4.2 Upper Bound for the Success Rate 5 Simulation Results 6 Summary References Microarchitectural Attacks A Bit-Level Approach to Side Channel Based Disassembling 1 Introduction 2 Background 2.1 Structure of a Side-Channel Disassembler 2.2 Related Work 3 Construction of a Bit-Level Side-Channel Disassembler 3.1 Challenges of Bit-Level Instruction Recovery 3.2 Leakage Model and Classification 3.3 From Signed Hamming Distance to Bit Values 3.4 Exploiting Local Information 4 Leakage Analysis of the PIC16F 4.1 Overview of the PIC16F 4.2 Our Experimental Setup 4.3 Study of Single Bit Leakages 5 Evaluation 5.1 Mono-Spatial Attack 5.2 Multi-spatial Attack 5.3 Template Portability 6 Conclusion and Further Work References CCCiCC: A Cross-Core Cache-Independent Covert Channel on AMD Family 15h CPUs 1 Introduction 2 Background 2.1 Microarchitecture 2.2 Processing of an Instruction in AMD Family 15h Piledriver CPUs 3 Related Work on Cache-Independent Information Leakage 4 Our Cache-Independent Covert Channels on AMD Family 15h 4.1 CCCiCC v1: Instruction Decoder Throughput 4.2 CCCiCC v2: Timing Measurement Noise 4.3 Implementation 4.4 Throughput Measurements 4.5 From Instruction Throughput to Covert Channel 5 Summary References Design Considerations for EM Pulse Fault Injection 1 Introduction 2 Challenge 3 Probe Design 3.1 Near-Field Coupling 3.2 Experimental Validation 3.3 Results 4 Pulse Generator 4.1 Switching Element 4.2 Pulse Delay and Jitter 4.3 Power Supply 5 Example Design 5.1 EM Pulse Injection Platform 5.2 Experimental Results 6 Conclusions A The RLC Circuit B EM-Pulse Injection Circuit - Schematic References Cryptographic Primitives Lightweight MACs from Universal Hash Functions 1 Introduction 2 MAC Constructions from Universal Hash Functions 2.1 Universal Hash Functions 2.2 MAC Algorithms 3 Construction of Universal Hash Functions 3.1 Constructions for Short Messages 3.2 Composition and Extension 4 Improved Bounds with Permutations 5 Instantiating a Lightweight MAC 5.1 Choice of Universal Hash Function: XPoly 5.2 Choice of Field and Multiplication 6 A Concrete Instantiation: MAC611 6.1 Implementation Details 6.2 Choice of the Parameter 6.3 Security Bounds A Comparison of Security Bounds References FELICS-AEAD: Benchmarking of Lightweight Authenticated Encryption Algorithms 1 Introduction 2 The FELICS Framework and Its AEAD Extension 2.1 Overview of Modules 2.2 API for Authenticated Encryption 2.3 Target Devices and Evaluation Metrics 3 Analyzed AEAD Algorithms 4 Preliminary Results 5 Comparison with Other Benchmarking Tools 6 Conclusions and Final Remarks References Advances in Side-Channel Analysis A Comparison of 2-Test and Mutual Information as Distinguisherpg for Side-Channel Analysis 1 Introduction 1.1 Contribution 2 Background 2.1 2-Test and Distinguisher 2.2 Mutual Information Analysis 2.3 Implementation of 2-Test and MIA 2.4 Relation Between 2-Test and Mutual Information 2.5 Higher-Order CPA 3 Case Study 1: PRESENT Threshold Implementation 3.1 Results 4 Case Study 2: Smart Card 4.1 Measurements 4.2 Architecture 4.3 Countermeasures 4.4 Alignment 4.5 Key Recovery 4.6 2-Test Vs. MIA Vs. HOCPA 5 Conclusion References Key Enumeration from the Adversarial Viewpoint 1 Introduction 2 Problem Statement 3 Background 3.1 Entropy, Rank and Guessing Entropy 3.2 Key Rank Estimation 4 Using the Entropy to Approximate the Rank 5 Adapting the CHES 2017 Key-Less GE 6 Simulated and Real Experiments 6.1 Experimental Setups 6.2 Results 7 Discussion and Limitations 8 Conclusion A Error Bounds on the Histogram Estimations References Author Index