Silicon Systems For Wireless Lan

Contents
Foreword
Part-1 Design
	Chapter 1 System Architecture
		1.1 Introduction
		1.2 Wireless Communication Systems
			1.2.1 Mobile communication
			1.2.2 Long-range communication
			1.2.3 Mid-range communication
			1.2.4 Short-range communication
			1.2.5 Why do we focus on WLAN only?
		1.3 WLAN Transceiver Architecture
			1.3.1 WLAN MAC sublayer
			1.3.2 WLAN physical layer
		References
	Chapter 2 Digital Baseband
		2.1 Introduction
		2.2 Scrambling/Descrambling
		2.3 Channel Coding and Error Correction
			2.3.1 Error detection schemes
			2.3.2 Error correction codes
			2.3.3 Common metrics of FEC codes
			2.3.4 Block codes
			2.3.5 Convolutional codes
		2.4 Interleaving/Deinterleaving
		2.5 Mapping/Demapping
		2.6 Pilot Insertion
		2.7 IFFT/FFT
		2.9 Pulse Shaping
		2.10 Synchronization
		2.11 Channel Estimation
			2.11.1 Time-domain windowing
			2.11.2 Frequency-domain interpolation
			2.11.3 Selection of a comb-type estimator
			2.11.4 Decision-directed channel estimators
		2.12 Equalization
		References
	Chapter 3 Analog Front-End
		3.1 Introduction
			3.1.1 Basic concepts in communication
			3.1.2 Modulation schemes in IEEE 802.11bag/n/ac
		3.2 Specifying Transceiver
			3.2.1 IEEE 802.11 transmitter constraints
			3.2.2 IEEE 802.11 receiver constraints
		3.3 Transmitter Architecture
			3.3.1 Direct conversion transmitter
			3.3.2 Heterodyne transmitter
				3.3.2.1 Conventional architecture
				3.3.2.2 RF synthesizer sharing: Variable-IF Transmitter
				3.3.2.3 Digital IQ implementation: Real-IF Transmitter
			3.3.3 Polar transmitter
		3.4 Receiver Architectures
			3.4.1 Direct conversion
				3.4.1.1 Pros and Cons
				3.4.1.2 Non-ideal Effects and Countermeasures in the Architecture
			3.4.2 Heterodyne receiver
		References
Part-2 Modeling
	Chapter 4 System Models
		4.1 Introduction
		4.2 WLAN MAC Model
		4.3 WLAN Baseband Model
		4.4 What is Next?
		References
	Chapter 5 Digital Circuit Models
		5.1 Introduction
		5.2 General Purpose Processors
		5.3 Digital Signal Processors
			5.3.1 Scrambler/descrambler
			5.3.2 Interleaver/deinterleaver
			5.3.3 Convolutional encoder and Viterbi decoder
			5.3.4 Constellation mapper/demapper
			5.3.5 Pilot insertion and pulse shaping
			5.3.6 IFFT/FFT processor
			5.3.7 Time and frequency synchronizer
			5.3.8 Channel estimator
		5.4 System Bus
		5.5 Memory Controller
		5.6 Debug Support Unit
		5.7 Peripherals
		References
	Chapter 6 AMS Circuit Budgets
		6.1 Introduction
		6.2 From High-Level Specifications to Low(er)-level Requirements
			6.2.1 Block-level metrics
				6.2.1.1 Noise metrics
				6.2.1.2 Distortion metrics
				6.2.1.3 Signal definition
			6.2.2 Error sources
				6.2.2.1 The receiver case
				6.2.2.2 The transmitter case
		6.3 Budgeting the Transceiver
		References
	Chapter 7 Embedded Memories
		7.1 Introduction
		7.2 Memory Systems: Current Landscape
			7.2.1 Embedded memory
			7.2.2 Alternatives to current memory landscape
			7.2.3 Memory hierarchy
		7.3 Memory Technologies
			7.3.1 SRAM
			7.3.2 DRAM
			7.3.3 Flash
			7.3.4 Emerging memory technologies
				7.3.4.1 PCM
				7.3.4.2 STT-RAM
				7.3.4.3 RRAM
		7.4 Conclusion
		References
Part-3 Implementation and Integration
	Chapter 8 Implementation Methodologies
		8.1 Introduction
		8.2 Semi-Custom Methodology
			8.2.1 ASIC implementation flow
			8.2.2 FPGA implementation flow
		8.3 Full-Custom Methodology
		References
	Chapter 9 Semi-Custom Implementation of Digital Circuits
		9.1 Introduction
		9.2 MAC Processor
		9.3 Digital Baseband Processor
		References
	Chapter 10 Full-Custom Implementation of Analog and Mixed-Signal Circuits
		10.1 Introduction
		10.2 Technology Selection
			10.2.1 RF considerations
			10.2.2 Baseband considerations
		10.3 AMS-RF Top-Level Implementation
			10.3.1 Modern full-custom design flow
			10.3.2 Analog and digital co-simulation
			10.3.3 Layout considerations
			10.3.4 Co-simulation with package and PCB models
		References
	Chapter 11 Integration
		11.1 Introduction
		11.2 Package Technology
			11.2.1 System-on-Chip (SoC)
				11.2.1.1 Packaging
				11.2.1.2 Horizontal extension
				11.2.1.3 Vertical extension
			11.2.2 System-In-Package (SiP)
		11.3 Antennas
			11.3.1 Antenna metrics
			11.3.2 Selection of antenna type
		11.4 RF-MIMO Transceiver Example
			11.4.1 Analog front-end
			11.4.2 Baseband processor
			11.4.3 MAC processor
			11.4.4 System integration and test
		References
Part-4 Verification and Testing
	Chapter 12 Verification
		12.1 Introduction
			12.1.1 Verification Plan
				12.1.1.1 Stimuli generation
				12.1.1.2 Response checking
			12.1.2 Verification environment implementation, device bring-up and regression
			12.1.3 Static or formal
				12.1.3.1 Automated theorem proving
				12.1.3.2 Model checking
				12.1.3.3 Equivalence checking
			12.1.4 Dynamic or Simulation-based
			12.1.5 Code coverage metrics
			12.1.6 Metrics based on the device activity
			12.1.7 Metrics based on FSM
			12.1.8 Error-based coverage metrics
			12.1.9 Typical UVM Testbench architecture
				12.1.9.1 UVM Test
				12.1.9.2 UVM Environment
				12.1.9.3 UVM Scoreboard
				12.1.9.4 UVM Agent
				12.1.9.5 UVM Sequencer
				12.1.9.6 UVM Sequence
				12.1.9.7 UVM Driver
				12.1.9.8 UVM Monitor
			12.1.10 UVM Class library
		Conclusions
		References
	Chapter 13 Digital Testing
		13.1 Introduction
		13.2 Test for What? Defects and Fault Modelling
		13.3 Which Test Sequence Do I have to Apply? Test Generation
			13.3.1 Fault Manager
			13.3.2 TPG Algorithm
				13.3.2.1 Sensitization
				13.3.2.2 Propagation
				13.3.2.3 Justification
			13.3.3 Fault Simulation
				13.3.3.1 PI1@0
				13.3.3.2 PI2@1
				13.3.3.3 G2/b@1
		13.4 How the Test Sequence is Applied? Design-for-Test
		13.5 Conclusions
		References
	Chapter 14 Analog, Mixed-Signal, and RF Circuits Test
		14.1 Introduction
		14.2 System-Level Considerations
			14.2.1 A generic approach: Analog test-bus
			14.2.2 An approach for transceivers: Loop-back
		14.3 Performance-Oriented Testing
			14.3.1 Design-for-testability and built-in self-test
				14.3.1.1 RF blocks
				14.3.1.2 Baseband circuits
			14.3.2 Machine-learning indirect test
		14.4 Defect-Oriented Testing
			14.4.1 Simulation
				14.4.1.1 Defect models
				14.4.1.2 Defect simulation
			14.4.2 Generic defect-oriented approaches
				14.4.2.1 IDDQ
				14.4.2.2 DC probes
				14.4.2.3 OBT
		References
	Chapter 15 Embedded Memory Test
		15.1 Introduction
		15.2 SRAM Memory Test
			15.2.1 Describing faulty behaviors
			15.2.2 Representation of functional faults
			15.2.3 Classification of faults
			15.2.4 Test solutions and algorithms
		15.3 Flash Memory Test
			15.3.1 Flash memory test flow
			15.3.2 Functional tests
			15.3.3 Reliability tests
			15.3.4 Repair strategies
		15.4 Test Challenges of Emerging Memories
			15.4.1 Test and reliability of PCMs
			15.4.2 Test and reliability of STT-MRAMs
			15.4.3 Test and reliability of RRAMs
		References
Index