Silicon based unified memory devices and technology

Content: PART I CONVENTIONAL SILICON BASED NVM DEVICES        1: SILICON BASED DIGITAL MEMORIES AND NVMs: AN INTRODUCTORY OVERVIEW        2: HISTORICAL PROGRESSION OF NVM DEVICES    2.1 FLOATING GATE DEVICES    2.2 CONVENTIONAL CHARGE TRAPPIN (CT) DEVICES    2.3 NANO CRYSTAL CHARGE TRAPPING NVMs (NC DEVICES)    2.4 DIRECT TUNNEL MEMORY (DTM)        3: GENERAL PROPERTIES OF DIELECTRICS AND INTERFACE FOR NVM DEVICES    3.1 ATTRIBUTES OF GATE STACKS FOR NVM DEVICES    3.2 GENERAL PROPERTIES OF THIN DIELECTRIC FILMS    3.3 INTERFACE PROPERTIES    3.4 GATE MATERIAL FOR NVM DEVICES        4: DIELECTRIC FILMS FOR NVM DEVICES    4.1 THERMAL OXIDE: SiO2    4.2 CVD or LPCVD NITRIDE: Si3N4    4.3 SILICON OXY-NITRIDES: SiONs    4.4 SILICON RICH INSULATORS: (SROs and SRNs)        5: NVM UNIQUE DEVICE PROPERTIES    5.1 MEMORY WINDOW W    5.2 MEMORY RETENTION    5.3 MEMORY ENDURANCE        6: NVM DEVICE STACK DESIGN    6.1 FUNDAMENTALS    6.2 FG NAND FLASH DEVICES: STACK/CELL DESIGN:    6.3 CHARGE TRAPPING DEVICES: CELL / STACK DESIGNS:        7: NVM CELLS, ARRAYS AND DISTURBS    7.1 PRE-SILICON GATE TECHNOLOGY AND NVM CELLS    7.2 THE PRE-NAND FLASH NVM CELLS IN SILICON GATE TECHNOLOGY    7.3 THE NAND FLASH CELL    7.4 FLOATING GATE NOR CELLS AND ARRAYS    7.5 CHARGE TRAP NVM CELLS AND ARRAYS    7.6 DISTURBS AND MITIGATION IN NVM CELLS AND ARRAYS        8: NVM PROCESS TECHNOLOGY AND INTEGRATION SCHEME    8.1 SILICON GATE CMOS PROCESS TECHNOLOGY HISTORY    8.2 NVM-UNIQUE TECHNOLOGY INTEGRATION FEATURES    8.3 NVM PROCESS FLOW AND INTEGRATION SCHEME    8.4 NROM PROCESS FLOW AND INTEGRATION SCHEME        9: NVM DEVICE RELIABILITY    9.1 RELIABILITY ISSUES ASSOCIATED WITH GATE STACK DIELECTRIC ELEMENTS    9.2 SiO2 TUNNEL DIELECTRIC FILM RELIABILITY    9.3 RADIATION INDUCED INSTABILITY        10: CONVENTIONAL NVM CHALLENGES    10.1 SCALABILITY CHALLENGES OF CONVENTIONAL NVMs        PART II ADVANCED NVM DEVICES AND TECHNOLOGY        11: VOLTAGE SCALABILITY    11.1 WHY VOLTAGE SCALING    11.2 EARLY HISTORY OF VOLTAGE SCALING    11.3 RECENT DEVELOPMENTS IN VOLTAGE SCALING    11.4 CT DEVICES SONOS VOLTAGE SCALING         12: HIGH-K DIELECTRICS FILMS FOR NVM    12.1 HISTORICAL PERSPECTIVE    12.2 GENERAL REQUIREMENTS    12.3 COMMON HIGH K DIELECTRIC FILMS FOR NVM GATE    12.4 FET GATE INSULATOR REQUIREMENTS    12.5 GENERAL CONSIDERATIONS FOR GATE INSULATOR APPLICATIONS: FILMS OF Al2O3, ZrO2, HfO2, Ta2O5, AND TiO2     12.6 ALUMINA (Al2O3)    12.7 HAFNIA (HfO2)     12.8 ZIRCONIA (ZrO2)     12.9 TANTALUM OXIDE (Ta2O5) AND TITANIUM OXIDE (TiO2)    12.10 BI-METAL OXIDES AND ALUMINATES OF HAFNIUM AND ZIRCONIUM     12.11 ALUMINATES OF LANTHANIDES     12.12 NITRIDES AND OXYNITRIDES OF HAFNIUM AND ZIRCONIUM     12.13 HAFNIUM SILICON OXYNITRIDE (HfSiON)     12.14 COMPARISON OF BAND DIAGRAMS OF HfO2, HfSiON, ZrO2 and LaAlO3    12.15 COMMON HIGH K FILMS FOR NVM APPLICATIONS    12.16 REVIEW OF HIGH K DIELECTRIC FILM APPLIATIONS FOR CURRENT NVM DEVICES    12.17 APPLIABILITY OF HIGH K DIELECTRIC FILMS FOR NVM GATE STACK DESIGN     12.18 HIGH K FILMS FOR TUNNELING12.19 LEAKAGE AND RETENTION FOR HIGH K TUNNEL DIELECTRIC FILMS    12.20 HIGH K FILMS FOR CHARGE TRAPPING     12.21 HIGH K FILMS FOR CHARGE BLOCKING    12.22 DEVICE DESIGN OBJECTIVES AND DIELECTRIC SELECTION OPTIONS     12.23 OTHER POTENTIAL FUTURE HIGH K DIELECTRIC FILMS FOR NVM DEVICES     12.24 INTEGRATION OF HIGH K FILMS IN SILICON BASED CMOS NVM TECHNOLOGY         13: BAND ENGINEERING FOR NVM DEVICES    13.1 REVISITING BAND-DIAGRAM AND BAND-ENGNEERING FOR CONVENTIONAL NVMs    13.2 BAND ENGINEERING USING SINGLE AND MULTILAYER DIELECTRICS     13.3 BAND ENGINEERING OPTIONS FOR THICKER MULTILAYER TUNNEL DIELECTRICS    13.4 BAND ENGINEERING OPTIONS FOR DIRECT TUNNEL MULTILAYER TUNNEL DELECTRICS     13.5 APPLICATIONS OF BAND ENGINEERING FOR SPECIFIC NVM DEVICE ATTRIBUTES     13.6 BAND ENGINEERING FOR DIRECT TUNNEL NVM DEVICES     13.7 BAND ENGINEERING FOR MULTILEVEL (MLC) and MULTIFUNCTIONAL (MF) NVMs         14: ENHANCED TECHNOLOGY INTEGRATION FOR NVM    14.1 FUNCTIONAL INTEGRATION AT INTERCONNECT AND PACKAGING LEVELS    14.2 NVM INTEGRATION AT MEMORY LEVEL    14.3 INTEGRATION AT FRONT-END-OF-LINE (FEOL) LEVEL    14.4 NVM TECHNOLOGY /DEVICE INTEGRATION SCHEMES    14.5 NVM DEVICE TRANSITION AND INTEGRATION CHALLENGES    14.6 ADDRESSING NVM DEVICE/ARRAYS CHALLENGES AND INTEGRATION:         15: PLANAR MULTILEVEL STORAGE NVM DEVICES    15.1 FG to FG CAPACITIVE COUPLING (Cell to cell coupling: CCC) for MLC NAND Design:    15.2 GCR for MLC NAND DESIGN    15.3 FG-MLC CELL DESIGNS FOR MEMORY LEVELS, STABILITY, SENSE MARGIN AND RELIABILITY    15.4 ADVANCED TECHNOLOGY: FG-MLC EXTENDABILITY CHALLENGES    15.5 PLANAR & WRAP-AROUND FLOATING GATE FLASH DESIGNS: EXTENDABILITY ISSUES    15.6 CURRENT STATE-OF-THE-ART IN MLC FG-NAND FLASH DEVICE & PRODUCTS    15.7 PLANR CHARGE TRAPPING MLC DEVICES: ENHANCED SONOS/MONOS    15.8 PLANAR CHARGE-TRAPPING MNSC DEVICES AND EXTENDABILITY: MNSC NROM AND NAND    15.9 ENHANCED CT-MNSC DEVICES    15.10 FUTURE OF PLANAR MULTILEVEL STORAGE NVM TECHNOLOGY, DEVICE & PRODUCTS    15.11 MULTIPLANAR STACKABLE NAND DEVICES AND TECHNOLOGY    15.12 ADDRESSING CURRENT PLANAR MLC FG-NAND-FLASH / SSD LIMITATIONS & SCALABILITY ISSUES        16: NON PLANAR AND 3D DEVICES AND ARRAYS    16.1 NON-PLANAR MULTI-BIT/CELL VERTICAL CHANNEL CT-DEVICES     16.2 FINFET AND GATE-ALL-AROUND (GAA) NV DEVICES     16.3 SURROUND GATE NV DEVICES (SGT)     16.4 FULL 3D NV DEVICES AND ARRAYS         17: EMERGING NVMs & LIMITATIONS OF CURRENT NVM DEVICES    17.1 DEVICE LEVEL AND FUNCTIONAL LEVEL ATTRIBUTES OF DRAM, NVMs(SSDs) AND HDD    17.2 The NVM MARKET HORIZON AND DRIVING FACTORS     17.3 EMERGING CONTENDERS FOR CONVENTIONAL SILICON-BASED NVM MEMORIES    17.4 REQIREMENTS OF MEMORY ATTRIBUTES FOR FUTURE APPLICATIONS / SYSTEMS        18: ADVANCED SILICON-BASED NVM DEVICE CONCEPTS    18.1 DEVICE PARAMETER ENHANCEMENT CONSIDERATION    18.2 APPLICATION PARAMETER ENHANCEMENT CONSIDERATION    18.3 APPLICATION DRIVERS FOR EMBEDDED AND STAND-ALONE NVMs     18.4 FUNCTIONAL AND ARCHITECTURAL REQUIREMENTS AND GROUPING OF NROMS    18.5 NVM EMBEDDED DEVICE TYPES AND OPTIONS     18.6 NVM DEVICE INTEGRATION OPTIONS    18.7 NVM PRODUCT AND STACK DESIGN BASIC CONSIDERATION    18.8 Advanced NVM DEVICE AND ARRAY CONCEPTS     18.9 ADVANCED NVM DEVICES AND ARRAYS: Device Stack and Band Features    18.10 SCALABLE AND NON-PLANAR NROMs    18.11 MLS and DENSE NROM DESIGN CONCEPTS: BOTH PLANAR AND NON-PLANAR    18.12 ADVANCED NAND DESIGN CONCEPTS: PLANAR AND NON-PLANAR    18.13 ADVANCED NANO-CRYSTAL DEVICE CONCEPTS    18.14 OTHER ADVACED MLC NVM DEVICE CONCEPTS    18.15 MULTIFUNCTIONAL NVM DEVICES         PART III: SUM: SILICON BASED UNIFIED MEMORY        19: SUM PERSPECTIVE, DEVICE CONCEPTS AND POTENTIALS    19.1 SUM PERSPECTIVE: APPLICABILITY AND FUNCTIONALITY    19.2 SUM DEVICE CONCEPTS AND CLASSIFICATIONS:     19.3 SUM DEVICES AND ARRAYS IN MEMORY HIERARCHY    19.4 COMPARATIVE ATTRIBUTES OF SUM vs OTHER MEMORIES        20: SUM TECHNOLOGY    20.1 CONSIDERATION AND SELECTION OF DIELECTRIC FILMS FOR SUM DEVICES    20.2 INTEGRATION SCHEME FOR SUM TECHNOLOGY    20.3 STACK DESIGNS for SUM DEVICES        21: BAND ENGINEERING FOR SUM DEVICES    21.1 BAND ENGINEERING FOR USUM DEVICES     21.2 MULTI-MECHANISM-CARRIER-TRANSPORT (MMCT) USUM DEVICE    21.3 BAND ENGINEERING FOR MSUM DEVICES    21.4 BAND DIAGRAM ILLUSTRATIONS FOR MSUM DEVICES         22: UNIFUNCTIONAL SUM: THE USUM CELLS AND ARRAY    22.1 FBRAM USUM CELL    22.2 THE GDRAM USUM CELL     22.3 THE GTRAM USUM CELL    22.4 THE CPRAM USUM CELL     22.5 THE FET USUM CELLS        23: MULTIFUNCTIONAL SUM: THE MSUM CELLS AND ARRAYS    23.1 INTEGRATED DRAM-NVRAM MULTILEVEL AND MULTIFUNCTIONAL MSUM CELL    23.2 The BAND ENGINEERED DTM MSUM CELLS AND ARRAYS    23.3 OTHER CT-MSUM DEVICES:    23.4 URAM AND OTHER MULTIFUNCTIONAL SILICON-BASED MEMORIES        24: SUM FUNCTIONAL INTEGRATION, PACKAGING AND POTENTIAL APPLICATION    24.1 INTEGRATION AT SILICON TECHNOLOGY / CHIP LEVEL    24.2 INTEGRATION AT PACKAGING LEVEL    24.3 INTEGRATION AT LARGE SYSTEM LEVEL    24.4 INTEGRATION AT FUNCTIONAL AND ARCHITECTURAL LEVEL    24.5 Current NVM and DRAM Market: POTENTIAL SUM APPLICATIONS    24.6 ADVANCED APPLICATIONS