Progress in VLSI Design and Test: 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings

Front Matter....Pages -
An Efficient High Frequency and Low Power Analog Multiplier in Current Domain....Pages 1-9
Design of Push-Pull Dynamic Leaker Circuit for a Low Power Embedded Voltage Regulator....Pages 10-18
Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm....Pages 19-29
Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding....Pages 30-39
Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects....Pages 40-45
Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET....Pages 46-51
Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips....Pages 52-58
Post-bond Stack Testing for 3D Stacked IC....Pages 59-68
Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker....Pages 69-78
Design of High Speed Vedic Multiplier for Decimal Number System....Pages 79-88
An Efficient Test Design for CMPs Cache Coherence Realizing MESI Protocol....Pages 89-98
An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs....Pages 99-110
Arithmetic Algorithms for Ternary Number System....Pages 111-120
SOI MEMS Based Over-Sampling Accelerometer Design with ΔΣ Output....Pages 121-128
Design Optimization of a Wide Band MEMS Resonator for Efficient Energy Harvesting....Pages 129-138
Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin....Pages 139-146
Workload Driven Power Domain Partitioning....Pages 147-155
Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit....Pages 156-165
A High Speed, Low Jitter and Fast Acquisition CMOS Phase Frequency Detector for Charge Pump PLL....Pages 166-171
ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits....Pages 172-179
Comparison of OpAmp Based and Comparator Based Switched Capacitor Filter....Pages 180-189
Effect of Malicious Hardware Logic on Circuit Reliability....Pages 190-197
A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power....Pages 198-208
Reusable and Scalable Verification Environment for Memory Controllers....Pages 209-216
Design of a Fault-Tolerant Conditional Sum Adder....Pages 217-222
SEU Tolerant Robust Latch Design....Pages 223-232
Design of Content Addressable Memory Architecture Using Carbon Nanotube Field Effect Transistors....Pages 233-242
High-Speed Unified Elliptic Curve Cryptosystem on FPGAs Using Binary Huff Curves....Pages 243-251
A 4 × 20 Gb/s 2 9 -1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology....Pages 252-257
VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases....Pages 258-269
A Synthesis Method for Quaternary Quantum Logic Circuits....Pages 270-280
On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits....Pages 281-288
Delay Uncertainty in Single- and Multi-Wall Carbon Nanotube Interconnects....Pages 289-299
A Fast FPGA Based Architecture for Sobel Edge Detection....Pages 300-306
Speech Processor Design for Cochlear Implants....Pages 307-316
An Efficient Technique for Longest Prefix Matching in Network Routers....Pages 317-326
A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts....Pages 327-336
Test Data Compression for NoC Based SoCs Using Binary Arithmetic Operations....Pages 337-342
Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip....Pages 343-349
An Efficient Multiplexer in Quantum-dot Cellular Automata....Pages 350-351
Integrated Placement and Optimization Flow for Structured and Regular Logic....Pages 352-353
A Novel Symbol Estimation Algorithm for LTE Standard....Pages 354-356
Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance....Pages 357-359
A Novel Approach to Voltage-Drop Aware Placement in Large SoCs in Advanced Technology Nodes....Pages 360-363
Design and Implementation of Efficient Vedic Multiplier Using Reversible Logic....Pages 364-366
Design of Combinational and Sequential Circuits Using Novel Feedthrough Logic....Pages 367-369
Efficient FPGA Implementation of Montgomery Multiplier Using DSP Blocks....Pages 370-372
Independent Gate SRAM Based on Asymmetric Gate to Source/Drain Overlap-Underlap Device FinFET....Pages 373-374
VLSI Architecture for Spatial Domain Spread Spectrum Image Watermarking Using Gray-Scale Watermark....Pages 375-376
A Photonic Network on Chip with CDMA Links....Pages 377-378
Simulation Study of an Ultra Thin Body Silicon On Insulator Tunnel Field Effect Transistor....Pages 379-380
Routing in NoC on Diametrical 2D Mesh Architecture....Pages 381-382
Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology....Pages 383-392
Power Problems in VLSI Circuit Testing....Pages 393-405
Back Matter....Pages -