Principles of Verilog Digital Design

Cover
Half Title
Title Page
Copyright Page
Contents
Preface
Acknowledgments
Chapter 1: Introduction
	1.1. Integrated Circuit Industry
	1.2. Digital Era
		1.2.1. A/D and D/A Conversion
		1.2.2. Digital Systems and Digital Logic
	1.3. Boolean Algebra and Logic Design
	1.4. Computer-Aided Design
	1.5. ASIC Design Flow
	1.6. Hardware Description Language
	1.7. Design Entry Based on Register-Transfer Level
	1.8. Functional Verification
	1.9. Logic Synthesis
	1.10. Timing Verification
		1.10.1. Dynamic Timing Analysis
		1.10.2. Static Timing Analysis
	1.11. Physical Design
		1.11.1. Design Implementation
	1.12. More on Design Flow
	1.13. Further Reading
	Problems
Chapter 2: Fundamentals of Verilog
	2.1. Introduction to Verilog HDL
	2.2. Module and Port
	2.3. Number Representation of Verilog
	2.4. Data Type
		2.4.1. Nets
		2.4.2. Registers
		2.4.3. Parameters
		2.4.4. Choosing Data Types for Ports
	2.5. Continuous Assignment
	2.6. Procedural Construct
		2.6.1. Initial Block
		2.6.2. Always Block
		2.6.3. Named Block of Procedural Construct
	2.7. Verilog Primitives
	2.8. Expression
		2.8.1. 2’s Complement Number
		2.8.2. Operand
		2.8.3. Operators
			2.8.3.1. Arithmetic Operators
			2.8.3.2. Sign Operators
			2.8.3.3. Relational Operators
			2.8.3.4. Equality and Inequality Operators
			2.8.3.5. Logical Comparison Operators
			2.8.3.6. Logical Bit-Wise Operators
			2.8.3.7. Shift Operators
			2.8.3.8. Concatenation and Replication Operators
			2.8.3.9. Reduction Operators
			2.8.3.10. Conditional Operator
	2.9. Simulation Environment
	2.10. Further Reading
	Problems
Chapter 3: Advanced Verilog Topics
	3.1. Abstract Levels
	3.2. If-Else Statement
	3.3. Case, Casez, and Casex Statements
	3.4. For Loop Statement
	3.5. Function and Task
	3.6. Parameterized Design
	3.7. Delay in Circuits
		3.7.1. Load Reduction by Buffer
		3.7.2. Delay Modeling
			3.7.2.1. Delay Characterization
		3.7.3. Delay Control
		3.7.4. Path Delay
	3.8. Blocking and Non-Blocking Assignments
	3.9. Some Useful System Tasks
		3.9.1. Simulation
		3.9.2. I/O
		3.9.3. Timing Check
		3.9.4. Data Conversion
	3.10. Advanced Verilog Simulation
		3.10.1. Compiler Directive
		3.10.2. Timing Simulation
	3.11. Advanced Verilog Features
		3.11.1. ANSIC-C Style Port Declaration
		3.11.2. Generate Statement
	3.12. Further Reading
	Problems
Chapter 4: Number Representation
	4.1. Precision and Resolution of a Number Representation
	4.2. Fixed-Point Numbers
		4.2.1. Representation
			4.2.1.1. Binary to Decimal Number Conversion
			4.2.1.2. Decimal to Binary Number Conversion
			4.2.1.3. Digital Signal Processing Applications
		4.2.2. Operations
			4.2.2.1. Addition Operation
			4.2.2.2. Multiplication Operation
			4.2.2.3. Signal Processing
	4.3. Floating-Point Numbers
	4.4. Other Binary Numbers
	4.5. Further Reading
	Problems
Chapter 5: Combinational Circuits
	5.1. Dataflow Description
	5.2. Behavioral Description
	5.3. Structural Description
	5.4. Combinational Loop
	5.5. Basic Building Blocks of Combinational Circuits: Logic Units
		5.5.1. Multiplexer
		5.5.2. Demultiplexer
		5.5.3. Comparator
		5.5.4. Shifter and Rotator
		5.5.5. Encoder
		5.5.6. Priority Encoder
		5.5.7. Decoder
		5.5.8. Bubble Sorting
	5.6. Basic Building Blocks of Combinational Circuits: Arithmetic Units
		5.6.1. Half Adder
		5.6.2. Full Adder
		5.6.3. Signed Arithmetic
			5.6.3.1. Fundamentals of Addition and Subtraction Using 2’s Complement
			5.6.3.2. Addition and Subtraction in 2’s Complement Using Verilog
			5.6.3.3. Multiplication in 2’s Complement Using Verilog
			5.6.3.4. Bit Width Design
			5.6.3.5. More on Overflow Detection
			5.6.3.6. Bit Width Design of Digital Signal Processing System
		5.6.4. Arithmetic Logic Unit
		5.6.5. Carry Look-Ahead Adder
		5.6.6. Complex Multiplier
		5.6.7. More on Sizing and Signing
	5.7. Further Reading
	Problems
Chapter 6: Sequential Circuits
	6.1. Introduction to Sequential Circuits
		6.1.1. Latch
		6.1.2. Flip-Flop
		6.1.3. Setup and Hold Times of Flip-Flops
		6.1.4. Master-Slave Flip-Flop
		6.1.5. Latch vs. Flip-Flop
	6.2. Behavioral Description
	6.3. Structural Description
	6.4. Basic Building Blocks of Sequential Circuits
		6.4.1. Registers
		6.4.2. Shift Registers
		6.4.3. Register Files
		6.4.4. State Machine
			6.4.4.1. State Reduction
			6.4.4.2. State Assignment
		6.4.5. Counter
			6.4.5.1. Synchronous Counter
			6.4.5.2. Asynchronous Counter
		6.4.6. FIFO
		6.4.7. Problems When Interacting with Signals from Different Procedural Blocks
	6.5. Further Reading
	Problems
Chapter 7: Digital System Designs
	7.1. System-Level Design: Moving from the Virtual to the Real
		7.1.1. Pipelined Design
		7.1.2. FIFO for Buffering Data
		7.1.3. Arbiter
		7.1.4. Interconnect
			7.1.4.1. Buses
			7.1.4.2. Crossbar Switches
			7.1.4.3. Interconnect Networks
	7.2. System-Level Design: Memory System
		7.2.1. Static Random-Access Memory
			7.2.1.1. More on Bidirectional Bus
			7.2.1.2. Asynchronous SRAM
		7.2.2. Read-Only Memory
	7.3. Architecture Design and Timing Diagram
		7.3.1. Complex Multiplier
		7.3.2. Two Additions
		7.3.3. Finite Impulse Response Filter
	7.4. Digital Design of Huffman Coding
		7.4.1. Block Diagram and Interface
		7.4.2. Algorithm Design
		7.4.3. RTL Design
	7.5. Further Reading
	Problems
Chapter 8: Advanced System Designs
	8.1. Dynamic Random-Access Memory
	8.2. Flash Memory
	8.3. Synchronizer Design
		8.3.1. Synchronization Failure
		8.3.2. Metastability
		8.3.3. Probability of Entering an Illegal State
		8.3.4. Simple Synchronizer
		8.3.5. Deterministic Multi-Bit Synchronizer
		8.3.6. Nondeterministic Multi-Bit Synchronizer Using FIFO without Flow Control
		8.3.7. Nondeterministic Multi-bit Synchronizer Using FIFO with Flow Control
	8.4. Computer Organization
		8.4.1. Embedded Processor
		8.4.2. Instructions and Data
		8.4.3. Crypto Processor
			8.4.3.1. AES Algorithm
			8.4.3.2. Processor Design
			8.4.3.3. RTL Design
			8.4.3.4. AES in Assembly
	8.5. Digital Design of Component Labeling Engine
		8.5.1. Block Diagram and Interface
		8.5.2. Algorithm Design
		8.5.3. RTL Design
	8.6. Further Reading
	Problems
Chapter 9: I/O Interface
	9.1. I/O Controller
		9.1.1. Simple Processor
			9.1.1.1. RTL Design
			9.1.1.2. I/O Control Program in Assembly
	9.2. Buses
		9.2.1. Multiplexed Buses
		9.2.2. Tristate Buses
		9.2.3. Open-Drain Buses
	9.3. Serial Transmission Techniques
		9.3.1. Serial Transmission Protocols
		9.3.2. Timing Synchronization
	9.4. I/O Interface of Embedded Software
		9.4.1. Polling
		9.4.2. Interrupts
			9.4.2.1. Simple Processor with Interrupt
			9.4.2.2. Keypad I/O Controller with Interrupt
			9.4.2.3. Program with Interrupt in Assembly for Two I/O Controls
		9.4.3. Timer
	9.5. Accelerators
	9.6. Further Reading
	Problems
Chapter 10: Logic Synthesis with Design Compiler
	10.1. Design for Synthesis
	10.2. Design Flow Considering Synthesis
		10.2.1. Design Objects
		10.2.2. Reading Design
		10.2.3. Describing Design Environment
		10.2.4. Reporting and Analyzing Design
			10.2.4.1. Design Report
			10.2.4.2. Timing Report
			10.2.4.3. Area Report
			10.2.4.4. Power Report
		10.2.5. Saving Design
	10.3. Setting Design Constraints
		10.3.1. Optimization Constraints
			10.3.1.1. Creating Clock
			10.3.1.2. Clock Latency
			10.3.1.3. Clock Transition
			10.3.1.4. Clock Uncertainty
			10.3.1.5. Impacts of Clock Tree Modeling
			10.3.1.6. More on Impacts of Clock Tree Modeling
			10.3.1.7. Derived Clock
			10.3.1.8. Multiple Clock Design
			10.3.1.9. Propagated Clock after CTS
			10.3.1.10. Maximum Delay of a Combinational Circuit
			10.3.1.11. Timing Exceptions
		10.3.2. Design Rule Constraints
	10.4. Compiling Design
		10.4.1. Timing Optimization
		10.4.2. Area Optimization
		10.4.3. Power Optimization
			10.4.3.1. Power Model
			10.4.3.2. Clock Gating
			10.4.3.3. Dynamic Power Optimization
			10.4.3.4. Power Analysis
		10.4.4. Mapping Effort
		10.4.5. Solving Setup Time Violations
		10.4.6. Solving Hold Time Violations
		10.4.7. Solving Multiple Port Nets
		10.4.8. Solving Large For Loops
		10.4.9. Solving Naming Rules
	10.5. Adaptive Threshold Engine
	10.6. Further Reading
	Problems
Appendix A: Basic Logic Gates and User Defined Primitives
	A.1. Basic Logic Gates
	A.2. User Defined Primitives
	A.3. Further Reading
Appendix B: Non-Synthesizable Constructs
	B.1. Non-Synthesizable Verilog Statements
	B.2. Further Reading
Appendix C: Advanced Net Data Types
	C.1. Examples
	C.2. Further Reading
Appendix D: Signed Multipliers
	D.1. Synthesis of Signed Multipliers
	D.2. Further Reading
Appendix E: Design Principles and Guidelines
	E.1. Basic Principles
	E.2. Design Guidelines
	E.3. Other Coding And Naming Styles
	E.4. Further Reading
Index