Principles of power integrity for PDN design -- simplified : robust and cost effective design for high speed digital products

Content: Preface   xixAcknowledgments   xxviiAbout the Authors   xxixChapter 1  Engineering the Power Delivery Network   11.1  What Is the Power Delivery Network (PDN) and Why Should I Care?   11.2  Engineering the PDN   51.3  "Working" or "Robust" PDN Design   81.4  Sculpting the PDN Impedance Profile   121.5  The Bottom Line   14Reference   15Chapter 2  Essential Principles of Impedance for PDN Design   172.1  Why Do We Care About Impedance?   172.2  Impedance in the Frequency Domain   182.3  Calculating or Simulating Impedance   212.4  Real Circuit Components vs Ideal Circuit Elements   262.5  The Series RLC Circuit   302.6  The Parallel RLC Circuit   342.7  The Resonant Properties of a Series and Parallel RLC Circuit   362.8  Examples of RLC Circuits and Real Capacitors   422.9  The PDN as Viewed by the Chip or by the Board   462.10  Transient Response   522.11  Advanced Topic: The Impedance Matrix   562.12  The Bottom Line   66References   68Chapter 3  Measuring Low Impedance   693.1  Why Do We Care About Measuring Low Impedance?   693.2  Measurements Based on the V/I Definition of Impedance   703.3  Measuring Impedance Based on the Reflection of Signals   713.4  Measuring Impedance with a VNA   763.5  Example: Measuring the Impedance of Two Leads in a DIP   813.6  Example: Measuring the Impedance of a Small Wire Loop   863.7  Limitations of VNA Impedance Measurements at Low Frequency   893.8  The Four-Point Kelvin Resistance Measurement Technique   933.9  The Two-Port Low Impedance Measurement Technique   953.10  Example: Measuring the Impedance of a 1-inch Diameter Copper Loop   1023.11  Accounting for Fixture Artifacts   1053.12  Example: Measured Inductance of a Via   1093.13  Example: Small MLCC Capacitor on a Board   1143.14  Advanced Topic: Measuring On-Die Capacitance   1203.15  The Bottom Line   134References   136Chapter 4  Inductance and PDN Design   1374.1  Why Do We Care About Inductance in PDN Design?   1374.2  A Brief Review of Capacitance to Put Inductance in Perspective   1384.3  What Is Inductance? Essential Principles of Magnetic Fields and Inductance   1414.4  Impedance of an Inductor   1474.5  The Quasi-Static Approximation for Inductance   1504.6  Magnetic Field Density, B   1554.7  Inductance and Energy in the Magnetic Field   1594.8  Maxwell's Equations and Loop Inductance   1634.9  Internal and External Inductance and Skin Depth   1674.10  Loop and Partial, Self- and Mutual Inductance   1724.11  Uniform Round Conductors   1754.12  Approximations for the Loop Inductance of Round Loops   1794.13  Loop Inductance of Wide Conductors Close Together   1824.14  Approximations for the Loop Inductance of Any Uniform Transmission Line   1884.15  A Simple Rule of Thumb for Loop Inductance   1944.16  Advanced Topic: Extracting Loop Inductance from the S-parameters Calculated with a 3D Field Solver   1954.17  The Bottom Line   202References   204Chapter 5  Practical Multi-Layer Ceramic Chip Capacitor Integration   2055.1  Why Use Capacitors?   2055.2  Equivalent Circuit Models for Real Capacitors   2065.3  Combining Multiple Identical Capacitors in Parallel   2095.4  The Parallel Resonance Frequency Between Two Different Capacitors   2115.5  The Peak Impedance at the PRF   2155.6  Engineering the Capacitance of a Capacitor   2205.7  Capacitor Temperature and Voltage Stability   2225.8  How Much Capacitance Is Enough?   2255.9  The ESR of Real Capacitors: First- and Second-Order Models   2295.10  Estimating the ESR of Capacitors from Spec Sheets   2345.11  Controlled ESR Capacitors   2385.12  Mounting Inductance of a Capacitor   2405.13  Using Vendor-Supplied S-parameter Capacitor Models   2515.14  How to Analyze Vendor-Supplied S-Parameter Models   2545.15  Advanced Topics: A Higher Bandwidth Capacitor Model   2585.16  The Bottom Line   272References   274Chapter 6  Properties of Planes and Capacitors   2756.1  The Key Role of Planes   2756.2  Low-Frequency Property of Planes: Parallel Plate Capacitance   2786.3  Low-Frequency Property of Planes: Fringe Field Capacitance   2796.4  Low-Frequency Property of Planes: Fringe Field Capacitance in Power Puddles   2856.5  Loop Inductance of Long, Narrow Cavities   2906.6  Spreading Inductance in Wide Cavities   2926.7  Extracting Spreading Inductance from a 3D Field Solver   3046.8  Lumped-Circuit Series and Parallel Self-Resonant Frequency   3076.9  Exploring the Features of the Series LC Resonance   3126.10  Spreading Inductance and Source Contact Location   3156.11  Spreading Inductance Between Two Contact Points   3176.12  The Interactions of a Capacitor and Cavities   3256.13  The Role of Spreading Inductance: When Does Capacitor Location Matter?   3276.14  Saturating the Spreading Inductance   3326.15  Cavity Modal Resonances and Transmission Line Properties   3346.16  Input Impedance of a Transmission Line and Modal Resonances   3406.17  Modal Resonances and Attenuation   3436.18  Cavity Modes in Two Dimensions   3476.19  Advanced Topic: Using Transfer Impedance to Probe Spreading Inductance   3546.20  The Bottom Line   361References   362Chapter 7  Taming Signal Integrity Problems When Signals Change Return Planes   3637.1  Signal Integrity and Planes   3637.2  Why the Peak Impedances Matter   3647.3  Reducing Cavity Noise through Lower Impedance and Higher Damping   3677.4  Suppressing Cavity Resonances with Shorting Vias   3727.5  Suppressing Cavity Resonances with Many DC Blocking Capacitors   3837.6  Estimating the Number of DC Blocking Capacitors to Suppress Cavity Resonances   3877.7  Determining How Many DC Blocking Capacitors Are Needed to Carry Return Current   3937.8  Cavity Impedance with a Suboptimal Number of DC Blocking Capacitors   3977.9  Spreading Inductance and Capacitor Mounting Inductance   4017.10  Using Damping to Suppress Parallel Resonant Peaks Created by a Few Capacitors   4037.11  Cavity Losses and Impedance Peak Reduction   4087.12  Using Multiple Capacitor Values to Suppress Impedance Peak   4117.13  Using Controlled ESR Capacitors to Reduce Peak Impedance Heights   4147.14  Summary of the Most Important Design Principles for Managing Return Planes   4187.15  Advanced Topic: Modeling Planes with Transmission Line Circuits   4197.16  The Bottom Line   423References   425Chapter 8  The PDN Ecology   4278.1  Putting the Elements Together: The PDN Ecology and the Frequency Domain   4288.2  At the High-Frequency End: The On-Die Decoupling Capacitance   4308.3  The Package PDN   4408.4  The Bandini Mountain   4478.5  Estimating the Typical Bandini Mountain Frequency   4528.6  Intrinsic Damping of the Bandini Mountain   4568.7  The Power Ground Planes with Multiple Via Pair Contacts   4608.8  Looking from the Chip Through the Package into the PCB Cavity   4658.9  Role of the Cavity: Small Boards, Large Boards, and "Power Puddles"   4698.10  At the Low Frequency: The VRM and Its Bulk Capacitor   4768.11  Bulk Capacitors: How Much Capacitance Is Enough?   4798.12  Optimizing the Bulk Capacitor and VRM   4838.13  Building the PDN Ecosystem: The VRM, Bulk Capacitor, Cavity, Package, and On-Die Capacitance   4888.14  The Fundamental Limits to the Peak Impedance   4928.15  Using One Value MLCC Capacitor on the Board-General Features   4988.16  Optimizing the Single MLCC Capacitance Value   5028.17  Using Three Different Values of MLCC Capacitors on the Board   5078.18  Optimizing the Values of Three Capacitors   5118.19  The Frequency Domain Target Impedance Method (FDTIM) for Selecting Capacitor Values and the Minimum Number of Capacitors   5148.20  Selecting Capacitor Values with the FDTIM   5168.21  When the On-Die Capacitance Is Large and Package Lead Inductance Is Small   5218.22  An Alternative Decoupling Strategy Using Controlled ESR Capacitors   5278.23  On-Package Decoupling (OPD) Capacitors   5328.24  Advanced Section: Impact of Multiple Chips on the Board Sharing the Same Rail   5408.25  The Bottom Line   543References   545Chapter 9  Transient Currents and PDN Voltage Noise   5479.1  What's So Important About the Transient Current?   5479.2  A Flat Impedance Profile, a Transient Current, and a Target Impedance   5509.3  Estimating the Transient Current to Calculate the Target Impedance with a Flat Impedance Profile   5529.4  The Actual PDN Current Profile Through a Die   5539.5  Clock-Edge Current When Capacitance Is Referenced to Both Vss and Vdd   5589.6  Measurement Example: Embedded Controller Processor   5629.7  The Real Origin of PDN Noise-How Clock-Edge Current Drives PDN Noise   5659.8  Equations That Govern a PDN Impedance Peak   5729.9  The Most Important Current Waveforms That Characterize the PDN   5779.10  PDN Response to an Impulse of Dynamic Current   5799.11  PDN Response to a Step Change in Dynamic Current   5829.12  PDN Response to a Square Wave of Dynamic Current at Resonance   5859.13  Target Impedance and the Transient and AC Steady-State Responses   5899.14  Impact of Reactive Elements, q-Factor, and Peak Impedances on PDN Voltage Noise   5959.15  Rogue Waves   6029.16  A Robust Design Strategy in the Presence of Rogue Waves   6109.17  Clock-Edge Current Impulses from Switched Capacitor Loads   6139.18  Transient Current Waveforms Composed of a Series of Clock Impulses   6229.19  Advanced Section: Applying Clock Gating, Clock Swallowing, and Power Gating to Real CMOS Situations   6299.20  Advanced Section: Power Gating   6339.21  The Bottom Line   638References   640Chapter 10  Putting It All Together: A Practical Approach to PDN Design   64310.1  Reiterating Our Goal in PDN Design   64310.2  Summary of the Most Important Power Integrity Principles   64510.3  Introducing a Spreadsheet to Explore Design Space   65410.4  Lines 1-12: PDN Input Voltage, Current, and Target Impedance Parameters   65810.5  Lines 13-24: 0th Dip (Clock-Edge) Noise and On-Die Parameters   66110.6  Extracting the Mounting Inductance and Resistance   66510.7  Analyzing Typical Board and Package Geometries for Inductance   67410.8  The Three Loops of the PDN Resonance Calculator (PRC) Spreadsheet   67710.9  The Performance Figures of Merit   68210.10  Significance of Damping and q-factors   68510.11  Using a Switched Capacitor Load Model to Stimulate the PDN   69410.12  Impulse, Step, and Resonance Response for Three-Peak PDN: Correlation to Transient Simulation   69610.13  Individual q-factors in Both the Frequency and Time Domains   70310.14  Rise Time and Stimulation of Impedance Peak   71010.15  Improvements for a Three-Peak PDN: Reduced Loop Inductance of the Bandini Mountain and Selective MLCC Capacitor Values   71810.16  Improvements for a Three-Peak PDN: A Better SMPS Model   72210.17  Improvements for a Three-Peak PDN: On-Package Decoupling (OPD) Capacitors   72410.18  Transient Response of the PDN: Before and After Improvement   73110.19  Re-examining Transient Current Assumptions   73610.20  Practical Limitations: Risk, Performance, and Cost Tradeoffs   73910.21  Reverse Engineering the PDN Features from Measurements   74010.22  Simulation-to-Measurement Correlation   74710.23  Summary of the Simulated and Measured PDN Impedance and Voltage Features   75410.24  The Bottom Line   757References   759Index   761