Pll Performance, Simulation, and Design

PLL Basics......Page 10
Basic PLL Overview......Page 11
Basic PLL Operation and Terminology......Page 12
The PLL as a Frequency Synthesizer......Page 13
The Modern Phase Frequency Detector with Charge Pump and its......Page 14
Conclusion......Page 15
Analysis of the Phase/Frequency Detector......Page 16
Example of how the PFD works......Page 17
Analysis of The PFD for Two signals Differing in Frequency a......Page 18
The Phase/Frequency Detector Dead Zone......Page 20
References......Page 21
Dual Modulus Prescaler......Page 22
Quadruple Modulus Prescalers......Page 23
Conclusion......Page 24
Fractional N PLL Example Fractional N PLL Example......Page 25
Fractional N Example......Page 26
Fractional N Architectures......Page 27
Timing Diagram for Fractional Compensation......Page 28
Reference......Page 29
Delta Sigma PLL Architecture......Page 30
The First Order Delta Sigma Modulator......Page 31
Dithering......Page 32
Reference......Page 33
Phase Noise, Reference Spurs, and Lock Time as They Relate t......Page 34
RF System Parameters......Page 35
Output Signal from Mixer......Page 37
Conclusion......Page 38
PLL Performance and Simulation......Page 40
Introduction to Loop Filter Coefficients......Page 41
Active Loop Filter......Page 42
Filter Coefficients for Active Loop Filters (Standard Type)......Page 43
Calculation of Loop Filter Coefficients from Loop Filter Pol......Page 44
Conclusion......Page 46
Introduction of Transfer Functions......Page 47
Analysis of Transfer Functions......Page 48
A Few Words About Modulation......Page 50
The Rule for Scaling Components......Page 51
Conclusion......Page 52
The Definition of Spur Gain......Page 53
Output of the Charge Pump When the PLL is in the Locked Cond......Page 54
Spur Level vs. Leakage Currents and Comparison Frequency......Page 55
Pulse Related Spurs......Page 56
Demonstration of the Consistency of the BasePulseSpur......Page 57
Sample Variation of Spur Levels and Mismatch with Do voltage......Page 58
Spur Levels vs. Parameters if Loop Filter is NOT Redesigned......Page 59
Reference Spurs and their Harmonics for Filter B......Page 60
Conclusion......Page 61
Derivation of Spurious Spectrum......Page 62
Spur Level, Modulation Index, and Frequency Variation......Page 63
References......Page 64
Theoretical calculation for BaseLeakageSpur = 19.9 dBc/Hz......Page 65
VCO Frequency Output......Page 66
Rolloff......Page 67
Mathematical Calculation of Uncompensated Fractional Spurs......Page 68
Fractional Spur Chart......Page 69
Calculated First Fractional Spur......Page 71
Calculated Second Fractional Spur......Page 72
Calculated Third Fractional Spur......Page 73
Measurement of Fractional Spurs Explanation......Page 74
Measured In-Band Fractional Spurs......Page 75
Uncompensated Fractional Spur Model......Page 76
Compensated Fractional Spurs......Page 77
Delta Sigma Sub-Fractional Spurs......Page 78
Conclusion......Page 79
Tips for Good Decoupling and Good Layout......Page 80
External Cross Talk Spur......Page 81
Crystal Reference Cross Talk Spur......Page 82
A Typical Crystal Oscillator Circuit......Page 83
Phantom Reference Spur......Page 84
Prescaler Miscounting Spur......Page 85
VCO Harmonic Spurs......Page 86
Conclusion......Page 87
1 Hz Normalized Phase Noise Floor (PN1Hz)......Page 88
Adding in the 1/f Noise into the PLL Noise Estimate......Page 89
Unshaped Phase Noise Example with the LMX2470......Page 90
Accounting for the VCO Noise......Page 91
Phase Noise Constants for Various National PLLs......Page 92
1 Hz Normalized Phase Noise Floor for Various National Semic......Page 93
Close In PLL Noise Example......Page 94
More Issues with Phase Noise Modeling and Measurement......Page 95
References......Page 96
Appendix A: Phase Noise for Resistors and Active Devices......Page 97
Illustration of RMS Phase Error of a Signal in the Time Doma......Page 99
RMS Phase Error Calculation from Frequency Domain......Page 100
Typical Phase Noise Spectral Plot for a PLL......Page 101
RMS Phase Error Interpretation in the Constellation Diagram......Page 102
Other Interpretations of RMS Phase Error......Page 103
Signal to Noise Ratio (SNR)......Page 104
Conclusion......Page 105
Second Order Approximation to Transient Response......Page 106
Classical Model for the Transient Response of a PLL......Page 108
Relationship Between Phase Margin, Damping Factor and Natura......Page 109
Fourth Order Transient Analysis......Page 110
Additional Comments Regarding the Lock Time Formula......Page 111
Simulation Results......Page 113
Actual Peak Time of 90 uS to 908.0 MHz......Page 114
Conclusion......Page 115
Appendix......Page 117
Deriving the Equations......Page 119
Discrete Lock Time Formulae......Page 121
Cycle Slipping......Page 122
Calculating the time to the First Cycle Slip for an Infinite......Page 123
Cycle Slip Example......Page 125
Formation of a Routh Table......Page 126
Routh Table for Second Order Loop Filter......Page 127
Third Order Routh Stability Table......Page 128
Fourth Order Routh Stability Table......Page 129
References......Page 130
Introduction......Page 131
VCO Noise......Page 136
PLL Design......Page 144
Choosing the Phase Margin, Loop Bandwidth, and Pole Ratios......Page 146
Impedance Parameters for Various Filter Orders......Page 147
Determining the Time Constants......Page 148
References......Page 149
A Second Order Passive Loop Filter......Page 150
Reference......Page 151
Solve For Components......Page 152
Third Order Passive Loop Filter......Page 154
Loop Filter Calculation......Page 155
Proof for the Optimal Choice of C1 and Verification it Leads......Page 157
References......Page 159
Appendix A:  A Third Order Loop Filter Design......Page 160
Fourth Order Passive Loop Filter......Page 162
Solution of Component Values from Time Constants......Page 164
References......Page 167
Appendix A:  A Fourth Order Loop Filter Design......Page 168
The Pole Switching Trick......Page 172
Feedback Approaches......Page 173
An Active Filter Using the Standard Feedback Approach......Page 174
Slow Slew Rate Modification to Standard Feedback Approach......Page 175
Third Order Alternative Feedback Active Filter Using Transis......Page 176
Loop Filter Impedance and Forward Loop Gain......Page 177
Calculating the Loop Filter Components......Page 178
References......Page 179
Active Filter Topology Used......Page 182
Loop Filter Time Constants and Component Values......Page 183
Reference......Page 184
Basic Passive Loop Filter Topology......Page 185
Reference Spur Gain vs. Various Loop Filter Parameters......Page 188
Spur Improvement for Various Order Filters Above a Second Or......Page 189
Choosing T31 and T43 for a 4th Order Filter......Page 190
Comment Regarding Active Filters......Page 191
Conclusion......Page 192
Definition of the Gamma Optimization Parameter......Page 193
Conditions for Simulations......Page 194
Lock Time as a Function of Phase Margin and Gamma......Page 195
Gamma and Phase Margin Values that Minimize Lock Time......Page 196
Conclusion......Page 197
Second Order Filter Using Fastlock......Page 198
The Fastlock Disengagement Glitch......Page 199
Fastlock Disengagement Glitch......Page 200
Disadvantages of Using Fastlock......Page 201
Cycle Slip Reduction......Page 202
Impact of Cycle Slip Reduction On Peak Time......Page 203
References......Page 204
The No Switched Component Filter......Page 205
Full Switched Loop Filter......Page 206
Conclusion......Page 208
The Advanced Rounding Method for a Passive Loop Filter......Page 209
Dealing With Capacitor Dielectrics......Page 211
Conclusion......Page 212
Additional Topics......Page 214
Lock Detect Circuit Construction and Analysis......Page 215
Lock Detect Pin Output for a PLL in the Locked State......Page 216
Lock Detect Circuit......Page 217
Lock Detect Circuit Design......Page 219
Typical Lock Detect  Circuit Design......Page 220
Typical Lock Detect Circuit Simulation......Page 221
Conclusion......Page 222
Calculation of Trace Impedance......Page 223
Problems with Having the Load Unmatched to the PCB Trace......Page 224
Impedance Matching Strategies......Page 225
Typical Impedance Matching Circuit......Page 226
Typical Resistive Pad......Page 227
High Frequency Capacitor Model......Page 228
References......Page 229
N Counter Determination......Page 230
On the Pitfalls of Sensitivity......Page 231
Typical Sensitivity Curve for a PLL......Page 232
PLL Locking to Wrong Frequency Due to R Counter Sensitivity......Page 233
Theoretical Maximum Tolerable Harmonics......Page 234
Maximum Tolerable Normalized Second Harmonic......Page 235
Common Problems and Debugging Techniques for PLLs......Page 236
Conclusion and Author’s Parting Remarks......Page 237
Supplemental Information......Page 238
Glossary and Abbreviation List......Page 239
Abbreviation List......Page 247
References......Page 249
Useful Websites and Online RF Tools......Page 250