Pipelined Analog to Digital Converter and Fault Diagnosis

PRELIMS.pdf
	Preface
	Acknowledgments
	Editor biography
		Alok Barua
	Contributor list
CH001.pdf
	Chapter 1 A 1.8 V, 10 bit, 500 mega samples per second parallel pipelined analog-to-digital converter
		1.1 Introduction
			1.1.1 Motivation and goal
			1.1.2 Chapter organization
		1.2 Pipelined analog-to-digital converter architecture
			1.2.1 Evolution of pipelined ADC architecture
			1.2.2 Flash architecture
			1.2.3 Two-step flash architecture
			1.2.4 Conventional pipelined ADC architecture
			1.2.5 Redundancy and digital correction
			1.2.6 The parallel pipelined ADC
		1.3 Operational transconductance amplifier (OTA)
			1.3.1 Introduction
			1.3.2 Requirement of gain
			1.3.3 Requirement of unity gain bandwidth (UGB)
			1.3.4 Folded cascode OTA
			1.3.5 Gain boosted folded cascode OTA
			1.3.6 Frequency response of a folded cascode OTA
			1.3.7 Results
		1.4 Sample-and-hold amplifier
			1.4.1 Introduction
			1.4.2 Noise issues in S&H circuits
			1.4.3 Flip-around SHA
			1.4.4 Bandwidth of the SHA
			1.4.5 Results
		1.5 Multiplying digital-to-analog converter (MDAC)
			1.5.1 Introduction
			1.5.2 Implementation and working principles
			1.5.3 Bandwidth limitations of an MDAC
			1.5.4 Results
		1.6 Comparator
			1.6.1 Introduction
			1.6.2 Dynamic comparator
			1.6.3 Input pre-amplifier stage
			1.6.4 The latch
			1.6.5 Self-biased differential amplifier or complimentary self-differential amplifier (CSDA)
			1.6.6 Results
		1.7 Conclusion
			1.7.1 Summary
			1.7.2 Future work
		References
CH002.pdf
	Chapter 2 A built-in self-test for a 1.8 V, 8 bit, 125 mega samples per second pipelined analog-to-digital converter
		2.1 Organization of the chapter
		2.2 Specifications of the pipelined ADC
		2.3 Motivation and aims
		2.4 Pipelined ADC architecture
		2.5 A MATLAB model of the pipelined ADC
		2.6 Results obtained in the Cadence environment
		2.7 Built-in self-test (BIST) system
			2.7.1 A BIST scheme for an ADC
			2.7.2 Implementation of a code-width BIST scheme for testing pipelined ADCs
			2.7.3 An 8 bit edge triggered register
			2.7.4 An 8 bit subtractor
		2.8 Simulation of the pipelined ADC
		2.9 Future work
		References
CH003.pdf
	Chapter 3 Design of an oscillation-based built-in self-test system for a 1.8 V, 8 bit, 125 mega samples per second pipelined analog-to-digital converter
		3.1 Introduction
			3.1.1 Introduction to the BIST
			3.1.2 Literature review
			3.1.3 Motivation and aims
			3.1.4 Brief description of the work
			3.1.5 Chapter organization
		3.2 Oscillation-based BIST principles
			3.2.1 General BIST principles
			3.2.2 BIST basic test flow
			3.2.3 Basic BIST architecture
			3.2.4 Principles of oscillation-based built-in self-test
			3.2.5 Oscillation BIST principles for functional testing of ADCs
			3.2.6 Oscillation-based BIST architecture
			3.2.7 Determination of the static performance parameters of an ADC using the OBIST scheme
			3.2.8 Challenges in designing a BIST for a pipelined ADC
			3.2.9 OBIST full scheme
		3.3 Implementation of oscillation-based BIST
			3.3.1 Signal generator
			3.3.2 Control logic block
			3.3.3 Offset measurement block
			3.3.4 DNL–INL–gain error measurement block
			3.3.5 Missing code error detection block
			3.3.6 Monotonicity error detection block
		3.4 Introduction to ADC dynamic testing
			3.4.1 Introduction
			3.4.2 Lossless discrete integrator
			3.4.3 Analog sine generator
			3.4.4 Simulated results
		3.5 Conclusion
			3.5.1 Work performed
			3.5.2 Future scope of work
		References
CH004.pdf
	Chapter 4 An oscillation-based built-in self-test (BIST) system for dynamic performance parameter evaluation of an 8 bit, 100 MSPS pipelined ADC
		4.1 Introduction
			4.1.1 Introduction to BIST
			4.1.2 Literature review
			4.1.3 Motivation and aims
			4.1.4 Contributions of this chapter
			4.1.5 Chapter organization
		4.2 Oscillation-based BIST principles
			4.2.1 General BIST principles
			4.2.2 BIST basic test flow
			4.2.3 General BIST architecture
		4.3 Test stimulus generation
			4.3.1 Principles of on-chip stimulus generation
			4.3.2 Non-linear wave shaping circuit
			4.3.3 Analog filter
			4.3.4 Switched capacitor filter
		4.4 OTA-C filter
			4.4.1 Operational transconductance amplifier and capacitor filter
			4.4.2 Designing the OTA
		4.5 Dynamic parameter evaluation of a pipelined ADC
			4.5.1 Pipelined ADC
			4.5.2 Dynamic performance parameter evaluation
		4.6 Fault analysis using the BIST system
			4.6.1 Sources of error in a pipelined ADC
			4.6.2 Distortion by switching charge injection
			4.6.3 Distortion due to common thermal noise
			4.6.4 The effect of op-amp parameters in ADC
			4.6.5 Mismatch error of the capacitor
			4.6.6 Offset error of the comparator
			4.6.7 Gain error and offset error of the op-amp
		4.7 Preparation of the layout and post-layout simulations
			4.7.1 Preparation of the layout of the whole system
		4.8 Conclusion
			4.8.1 Future scope
		References
CH005.pdf
	Chapter 5 A reconfigurable built-in self-test architecture for a pipelined ADC
		5.1 Introduction
			5.1.1 Introduction to the built-in self-test (BIST)
			5.1.2 Literature review
			5.1.3 Motivation for this work
			5.1.4 Objective of the work
			5.1.5 Contributions to the work
			5.1.6 Organization of the chapter
		5.2 The pipelined ADC
			5.2.1 Background
			5.2.2 Introduction to pipelined ADCs
		5.3 Oscillation-based built-in self-test system
			5.3.1 General BIST principles
			5.3.2 Oscillation-based built-in self-test (OBIST) system
			5.3.3 Design of the current reference
			5.3.4 Measurement of oscillation frequency
			5.3.5 Schmitt trigger
			5.3.6 Control logic block
			5.3.7 DNL and INL measurement blocks
			5.3.8 Reconfigurability for detection of a faulty block in the ADC
		5.4 Implementation of the ADC and OBIST
			5.4.1 The pipelined ADC
			5.4.2 Design implementation of the blocks of the pipelined ADC
			5.4.3 Design implementation of OBIST
			5.4.4 Test bench
			5.4.5 Simulation results
			5.4.6 Diagnosis of a faulty block by reconfigurability
		5.5 Conclusion
			5.5.1 Work done
			5.5.2 Future work
		References