Open Radio Access Network (O-RAN) Systems Architecture and Design

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Open Radio Access Network (O-RAN) Systems Architecture and Design
Copyright Page
Contents
About the authors
Preface
Acronyms
1 Open radio access network overview
	The Open Radio Access Networks Alliance
		Open Radio Access Networks members
		Why now?
	On C-RAN, Open vRAN, OpenRAN, xRAN, and Telecommunications Infrastructure Project
	Spectrum: enabling 5G
		Licensed operator spectrum
		Licensed private spectrum
			United States
				Spectrum allocation system and related components
				Coexistence
			Europe (example: Germany)
			Japan
		Unlicensed spectrum
	Traditional base station architectures
		All-in-one base station
		3G/4G/5G macro cell
	5G base station architectures
		Integrated small cell
		Pico/micro cell
		Distributed antenna systems
		Massive multiple-input, multiple-output
		C-(as in: centralized) radio access network
	Functional splits
		Distributed versus centralized processing
			Fronthaul throughput
			Centralized processing features: Coordinated Multipoint Processing
	Coordinated Multipoint
		Open Radio Access Network-supported functional splits
			Central unit/distributed unit/radio unit
				Option 7–2x
				Relevant 3GPP standards
				nFAPI
				Other relevant standards
			Integrated small cell
	A real-life example: enterprise 5G networking
		Network installation and maintenance. Who will run the network?
		Who are the users of the network?
		What are the applications running on the network and what are derived key performance indicators?
		Total cost of ownership
		Use-case example
		RF aspects
	Summary and conclusions
	References
	Further reading
2 System components, requirements, and interfaces
	Next-Generation Radio Access Network overview and terminology
		Wired networking analogy
	Central unit
		Control plane user plane split and central unit/distributed unit interface
		Internet Protocol (IP) and Internet Protocol Security (IPSec)
		Quality of Service and related concepts
			Reflective Quality of Service
		Packet Data Convergence Protocol (PDCP)
		Dual and multiconnectivity
	Distributed unit
		F1 termination
		Radio Link Control and Medium Access Control
			Hybrid Automatic Repeat Request
			Power control
				Receive side
				Transmit side
			Discontinuous transmission and reception
			Semi-persistent scheduling
			Bandwidth adaptation/bandwidth part operation
			Supplementary Uplink operation
		Physical Layer
			Channel mapping
			Radio Network Temporary Identifier
			Numerology
			Channel coding (3GPP 38.212)
			Physical channel mapping and modulation (3GPP 38.211)
	Radio unit
		Generalized block diagram
		Digital beamforming and fast Fourier transform
		Digital up conversion, channelization, and digital down conversion
		Peak-to-average power ratio reduction and performance improvement techniques
			Crest factor reduction
			Digital predistortion
		Digital↔analog conversion (digital-to-analog converter/analog-to-digital converter) and analog components
		Analog gain control
		Time and frequency synchronization
		PRACH
	Distributed unit/radio unit interface, Enhanced Common Public Radio Interface protocol overview
	Initial access
		Synchronization
		Random-access procedure
	802.1CM
		Traffic classes
		Bridging functions
		Fronthaul profiles
	Fronthaul gateway
	Cell site router/gateway
	Form factor, environmental and power requirements
	ASN.1
	DiffServ
		Multiprotocol Label Switching support for DiffServ
	References
3 Hardware system dimensioning
	Centralized/distributed unit use-case dimensioning for throughput
		Traffic requirements based performance analysis
		User data rate dimensioning
		Elephant flows
	Use-case dimensioning for latency
	Users/transmission time interval
	eCPRI, fronthaul bandwidth and latency
		5G bandwidth examples
		4G bandwidth examples
		Fronthaul latency
	Distributed unit internal IO
	Memory dimensioning
		Memory sizing
		Life-of-a-packet memory bandwidth analysis
		HARQ memory and bandwidth dimensioning
			Transport blocks, code blocks, and HARQ
			Limited buffer rate matching
			On code block versus transport block level CRC
			Transmit operation
	HARQ process count dimensioning
	Radio unit
		Instantaneous bandwidth and occupied bandwidth
		Receiver chain analysis
		Radio unit latency and delay
		Digital predistortion
		Data converter and phase locked loop (PLL)
	References
	Further reading
4 Hardware architecture choices
	Scalability
	Development cycle
	Data center architecture
	Cell site integrated (CU/DU) solutions
		Server-based solutions
		Optimized hardware
	Radio unit
		eCPRI termination
		Low physical layer and digital front end
		Baseband to radio frequency conversion
		Digital-to-analog conversion and analog-to-digital conversion
		Radio frequency subsystem
			JESD
			Analog
		Sub 6GHz front end module
			Transmit
			Receive
			Control
		mmWave radio frequency module
			mmWave Link Budget Example
			Beam switch process steps
	Integrated small cell
		Networking processor/host
		Physical layer/5G modem
		Radio frequency subsystem
	Multicore central processing unit selection criteria
		Single instruction multiple data
		x86
		Arm
		Performance benchmarking
		Memory and I/O dimensioning
		Hardware offload
	PCIe performance
		Transaction layer packetization
		Example calculation
	References
5 System software
	Operating system
		Bare metal/RTOS versus embedded Linux
		Boot process and application load
		Long Term Support
		Roll your own versus commercial grade
		Realtime and timing
		Buffer and memory management
		Hardware acceleration model
		Bbdev and inter process communication
		Linux and processor performance tuning
	Networking stacks
		Features
		Security
		Performance
	Functional application platform interface
		PHY API
		nFAPI
		Network monitor mode API
	Security aspects
		Profiling
		Network reconnaissance
		Security updates
		Application architecture
		3GPP and International Electrotechnical Commission security requirements
	References
	Further reading
6 User-plane application components
	GTP Protocol
	PDCP protocol
		Robust header compression
	RLC Protocol
	MAC protocol
	eCPRI protocol overview
	Low physical layer
		Beamforming and time/frequency domain conversion
		PRACH extraction and filtering
	Digital front-end
		Signal aggregation and digital up conversion
		Crest factor reduction
		Digital Predistortion
		Receive side gain control
	References
	Further reading
7 Wireless scheduling and Quality of Service optimization techniques
	Orthogonal frequency division multiple access
		Orthogonal frequency division multiple access subcarrier allocation
		Modulation
	Base station scheduler algorithms
		Opportunistic scheduler
		The Quality of Service scheduler
		Combined Quality of Service and opportunistic schedulers
		Multiuser multiple input multiple output
	Architectural framework for the base station wireless scheduler algorithm
		Static and regular scheduling
		Active user selection
		Primary user selection (time-domain scheduling)
		Frequency allocation (frequency-domain scheduling)
		Secondary and remainder user(s) selection: multiple input multiple output scheduling
	System-level optimization
	Software optimization techniques
		Example: arg(max) vectorization
	References
	Further reading
8 Synchronization in open radio access networks
	Understanding frequency, time, syntonization, and synchronization
		Frequency
		Time and phase
		What is time?
		Syntonized versus synchronized
	How do we get time?
		Global navigation by satellite systems
	O-RAN synchronization
		Network-based synchronization
		Physical-layer transport and Synchronous Ethernet
		Packet time transport and precision time protocol
		An introduction to PTP
		Putting PTP and SyncE together
	Cellular network synchronization requirements
		Frequency accuracy and stability
		Time accuracy
	Synchronization in O-RAN
	O-RAN network-level synchronization
		FTS or PTS? SyncE or no SyncE
	O-RAN sync equipment requirements
	Sync solution implementation
		Frequency-only systems
		Time-synchronization systems
		Designing a PTP+SyncE solution
	The effects of timestamping location and resolution
		Oscillator selection and holdover
	Unraveling the standards spaghetti
	Further reading
9 Software performance
	Packet processing cycle budget analysis
		Example: Enhanced Common Public Radio Interface complexity analysis
	Physical Layer complexity analysis
		Phase 1: theoretical analysis
		Phase 2: performance proof points
		Phase 3: stack development
	Central Processing Unit loading summary
	System-on-Chip performance counters
	Life-of-a-packet double data rate utilization analysis
	Mitigation techniques: what if the product does not meet performance targets?
	Development environment optimization
	Software optimization techniques
	Reference
10 Interoperability and test
	Development testing
		Static analysis
		Functional
		Performance
	System test setup
		Feature testing
		RF compliance testing
			Transmitter
			Receiver
			Calibration
			Tools needed
		Interoperability testing
			Use-case scenarios
			User Equipment test pool
			Plug fest
		Consumer application hardening
	Performance testing
		Black box testing
			Throughput
			Latency
			Stability
			Cell performance
		White box testing
	Front-, mid-, and backhaul testing
	Operator acceptance testing
	Regulatory approval testing
	References
11 Differentiation by use case
	Ultra-reliable low-latency communication
		3GPP standards: ultra-reliable low-latency communication in 5G/NR
			Orthogonal frequency division multiplexing numerologies
			Slot/mini-slot structure
			Uplink grant-free transmission
			High reliability
			Interference management
		Deployment options including edge compute and software-defined networking
	Vehicle-to-infrastructure (vehicle-to-anything) roadside unit architecture and implementation
		Introduction
		Spectral aspects
		Vehicle-to-anything standards and deployment timeline
			802.11p
			4G C-V2X (PC5)
			NR C-V2X (PC5)
			Standards summary
			Deployment timeline
		Roadside unit
			System architecture
	5G Reduced Capabilities (RedCap)
		Reduced number of Rx/Tx antennas
		User Equipment bandwidth reduction
		Half-duplex Frequency Division Duplexing operation
		Relaxed User Equipment processing time
		Relaxed maximum number of multiple-input, multiple-output layers
		Relaxed maximum modulation order
		Combinations of abovementioned features
	References
	Further reading
Index
Back Cover