On-Chip Networks

Acknowledgments......Page 13
Communication Demands of Multi-Core Architectures......Page 15
Network Basics: A Quick Primer......Page 16
Evolution to On-Chip Networks......Page 17
Performance and Cost......Page 18
Commercial On-Chip Network Chips......Page 19
This Book......Page 20
Shared Memory Networks in Chip Multiprocessors......Page 23
Impact of Coherence Protocol on Network Performance......Page 24
Protocol-Level Network Deadlock......Page 26
Impact of Cache Hierarchy Implementation on Network Performance......Page 27
Home Node and Memory Controller Design Issues......Page 31
Miss and Transaction Status Holding Registers......Page 32
Synthesized NoCs in MPSoCs......Page 33
The Role of Application Characterization in NoC Design......Page 35
NoC Synthesis......Page 36
NoC Network Interface Standards......Page 38
Case Studies......Page 40
Brief State-of-the-Art Survey......Page 41
Metrics for Comparing Topologies......Page 43
Direct Topologies: Rings, Meshes and Tori......Page 46
Indirect Topologies: Butterflies, Clos Networks and Fat Trees......Page 47
Irregular Topologies......Page 49
Topology Synthesis Algorithm Example......Page 51
Layout and Implementation......Page 52
Concentrators......Page 53
Implication of Abstract Metrics on On-Chip Implementation......Page 54
Case Studies......Page 55
Brief State-of-the-Art Survey......Page 56
Types of Routing Algorithms......Page 59
Deterministic Dimension-Ordered Routing......Page 60
Oblivious Routing......Page 62
Adaptive Routing......Page 63
Adaptive Turn Model Routing......Page 64
Implementation......Page 66
Source Routing......Page 67
Node Table-Based Routing......Page 68
Adaptive Routing......Page 69
Routing on Irregular Topologies......Page 70
Brief State-of-the-Art Survey......Page 71
Messages, Packets, Flits and Phits......Page 73
Circuit Switching......Page 74
Store and Forward......Page 76
Wormhole......Page 77
Virtual Channels......Page 78
Deadlock-Free Flow Control......Page 81
Escape VCs......Page 82
Buffer Backpressure......Page 83
Buffer Sizing for Turnaround Time......Page 84
Reverse Signaling Wires......Page 85
Flow Control Implementation in MPSoCs......Page 87
Brief State-of-the-Art Survey......Page 88
Pipeline......Page 90
Pipeline Implementation......Page 92
Pipeline Optimizations......Page 93
Buffer Organization......Page 95
Crossbar Designs......Page 97
Crossbar Speedup......Page 98
Crossbar Slicing......Page 99
Round-Robin Arbiter......Page 100
Matrix Arbiter......Page 101
Separable Allocator......Page 102
Wavefront Allocator......Page 103
Allocator Organization......Page 104
Implementation......Page 105
Router Floorplanning......Page 106
Case Studies......Page 108
Brief State-of-the-Art Survey......Page 110
Definition of Ideal Interconnect Fabric......Page 111
Network Power-Delay-Throughput Gap......Page 112
Low-Power On-Chip Networks......Page 114
Beyond Conventional Interconnects......Page 115
NoC Infrastructures......Page 116
On-Chip Networks Conferences......Page 117
Bibliographic Notes......Page 118
Bibliography......Page 119
Biography......Page 141