Nonvolatile Memory Technologies with Emphasis on Flash: A Comprehensive Guide to Understanding and Using Flash Memory Devices (IEEE Press Series on Microelectronic Systems)

NONVOLATILE MEMORY TECHNOLOGIES WITH EMPHASIS ON FLASH......Page 4
CONTENTS......Page 8
Foreword......Page 20
Preface......Page 24
Contributors......Page 26
1.1 Introduction......Page 30
1.2 Elementary Memory Concepts......Page 31
1.3.1 Storage......Page 38
1.3.3 Retention......Page 41
1.4 Flash Memory and Flash Cell Variations......Page 42
1.5 Semiconductor Device Technology Generations......Page 45
References......Page 47
2.1 Introduction......Page 48
2.1.1 Spectrum of Memory Devices......Page 49
2.1.2 Evolving from EPROMs......Page 50
2.1.3 NOR and NAND......Page 51
2.1.4 Evolution of Flash Usage Models......Page 52
2.1.5 Understanding Flash Attributes......Page 54
2.2 Code Storage......Page 67
2.2.1 Execute-in-Place......Page 68
2.2.2 Store and Download......Page 72
2.2.4 Future Code Storage Applications......Page 74
2.3.2 Architectural Decisions......Page 75
2.3.3 Embedded Flash Storage......Page 78
2.3.4 Removable Media......Page 79
2.4 Code+Data Storage......Page 83
2.4.1 Relevant Attributes for Code+Data......Page 84
2.4.2 Fitting the Pieces Together for Code+Data......Page 87
2.4.3 Benefits of Code+Data......Page 90
2.5 Conclusion......Page 91
3.2 Flash Cell Basic Operation......Page 92
3.2.2 Cell Erase......Page 93
3.2.4 Read......Page 94
3.3 Flash Memory Architecture......Page 95
3.3.1 Memory Cell Array......Page 98
3.3.2 Analog Blocks......Page 100
3.3.3 Control Logic......Page 102
3.4.2 Yield Improvement......Page 104
3.4.3 Yield Simulator......Page 106
3.4.4 Redundancy Fuses Design......Page 107
3.4.5 Row Redundancy Design......Page 108
3.4.6 Column Redundancy Design......Page 109
3.4.7 Advanced Redundancy Design......Page 110
3.5 Error Correction Coding (ECC)......Page 116
3.5.1 On-Chip ECC and Endurance/Retention in Flash Memories......Page 117
3.6 Design for Testability (DFT)......Page 118
3.6.1 Test Entry and Organization......Page 120
3.6.2 Fuse Cell......Page 121
3.6.3 Sense Amplifier Reference Trimming and Monitor......Page 122
3.6.4 High Voltages Trimming......Page 123
3.6.5 Timings Trimming and External Control......Page 125
3.6.6 Internal State Machine Algorithm Skips and Monitor......Page 126
3.6.7 Address Path Configuration......Page 127
3.6.8 Data Path Configuration and Trimming......Page 128
3.6.9 High Voltages External Forcing and Monitor......Page 130
3.6.10 Array Direct Access and Stresses......Page 132
3.6.11 Internal Pattern Write and Verify......Page 134
3.6.12 Data Compression......Page 135
3.7 Flash-Specific Circuit Techniques......Page 137
3.7.1 Voltage Level Shifting......Page 138
3.7.2 Sensing......Page 141
3.7.3 Voltage Multiplication......Page 143
3.7.4 Reference Voltage Generation......Page 147
3.7.5 Voltage Regulation......Page 148
3.7.6 I/O Signal Buffering......Page 151
References......Page 152
4.1 Introduction......Page 158
4.2.1 Floating-Gate Principle......Page 159
4.2.2 Basic Definitions with Examples......Page 160
4.2.3 Basic Equations and Models......Page 169
4.3 Physics of Programming and Erase Mechanisms......Page 172
4.3.1 Fowler–Nordheim Tunneling......Page 174
4.3.2 Polyoxide Conduction......Page 177
4.3.3 Channel Hot-Electron Injection (CHEI)......Page 179
4.3.4 Substrate Hot-Electron Injection (SHEI)......Page 182
4.3.5 Source-Side Injection (SSI)......Page 184
4.3.6 Secondary Impact Ionization Initiated Channel Hot-Electron Injection......Page 185
4.4.1 Band-to-Band Tunneling......Page 187
4.4.2 Oxide Degradation......Page 188
4.4.3 Oxide Breakdown......Page 197
4.5 Conclusion......Page 200
References......Page 201
5.1 Introduction......Page 208
5.2.2 Cell Structure......Page 209
5.2.3 Read (Sensing)......Page 211
5.2.5 Erasing......Page 212
5.2.6 Array Operation......Page 215
5.2.7 Erase Threshold Control......Page 216
5.2.8 Process and Scaling Issues......Page 219
5.2.9 Key Circuits and Circuit/Technology Interactions......Page 229
5.3.1 Introduction......Page 235
5.3.2 Cell Cross Sections and Layout......Page 236
5.3.3 Charge Transfer Mechanisms......Page 237
5.3.4 Erase......Page 238
5.3.5 Programming......Page 239
5.3.6 Cell Array Architecture and Operation......Page 241
5.3.8 Process Scaling Issues......Page 243
5.3.9 Key Circuit Interactions......Page 244
5.4.1 Oxide Integrity......Page 245
5.4.3 Data Retention......Page 246
5.4.4 Endurance......Page 247
5.4.5 Disturbs......Page 248
References......Page 249
6.1 Overview of NAND EEPROM......Page 252
6.2.2 Erase Operation......Page 256
6.2.3 Program Operation......Page 257
6.2.4 Program Disturb......Page 258
6.2.5 Read Operation......Page 259
6.3.1 Staggered Row Decoder......Page 260
6.3.2 Self-Boosted Erase Inhibit Scheme......Page 262
6.3.3 Self-Boosted Program Inhibit Scheme......Page 264
6.4.1 Bit-by-Bit Verify Circuit......Page 266
6.4.2 Sophisticated Bit-by-Bit Verify Circuit......Page 271
6.4.3 Overprogram Elimination Scheme......Page 276
6.5.1 Shallow Trench Isolation NAND Technology (256-Mbit NAND)......Page 281
6.5.2 Booster Plate Technology......Page 285
6.5.3 Channel Boost Capacitance Cell......Page 287
6.5.4 Negative V(th) Cell......Page 292
6.5.5 Free Wordline Spacing Cell......Page 297
6.6.1 Shielded Bitline Sensing Method......Page 299
6.6.2 Full Chip Burst Read Operation......Page 301
6.6.3 Symmetric Sense Amplifier with Page Copy Function......Page 302
6.6.4 Source Line Programming Scheme......Page 307
6.7.1 Multilevel Circuit Technology......Page 312
6.7.2 Array Noise Suppression Technology......Page 315
6.7.3 Side-Wall Transfer Transistor Cell......Page 322
6.7.4 Three-Level NAND......Page 326
6.7.5 High-Speed Programming......Page 330
References......Page 336
Bibliography......Page 339
7.2.1 DINOR Operation......Page 342
7.2.2 DINOR Cell Characteristics......Page 343
7.2.4 DINOR Advanced Array Architecture......Page 345
7.2.5 VGA-DINOR Device Structure and Fabrication......Page 346
7.2.6 Characteristics of the Cell with Asymmetrical Offset Source/Drain Structure......Page 347
7.3.1 Low-Voltage Read......Page 349
7.4.1 High-Voltage Generation [7]......Page 350
7.4.2 Wordline Boost Scheme......Page 355
7.5.2 Emulating Electrically Erasable Programmable Read-Only Memory (EEPROM) and Static Random-Access Memory (SRAM)......Page 356
7.6.1 Introduction......Page 357
7.6.2 Band-to-Band Hot-Electron Injection Cell Operation......Page 358
7.6.3 DINOR BBHE Programmed Cell......Page 361
References......Page 363
Bibliography......Page 364
8.1 Introduction......Page 366
8.3 Operations of P-Channel Flash......Page 367
8.4.1 NOR-Type Array Architecture......Page 372
8.4.2 NAND-Type Array Architecture......Page 373
8.5.1 Hsu et al. [1]......Page 374
8.5.2 Ohnakado et al. [4]......Page 378
8.5.3 Ohnakado et al. [5]......Page 379
8.5.5 Chung et al. [7]......Page 382
8.5.6 Sarin et al. [8]......Page 383
8.5.7 Wang et al. [9]......Page 386
8.5.8 Ohnakado et al. [2]......Page 388
8.5.9 For Further Study......Page 391
8.6 Processing Technology for P-Channel Flash......Page 395
8.6.1 NOR-Type Array Architecture......Page 396
8.6.2 NAND-Type Array Architecture......Page 397
References......Page 399
Bibliography......Page 400
9.1 Introduction......Page 402
9.2.1 Advantages of Embedded over Stand-Alone Flash Memory......Page 404
9.2.2 Disadvantages of Embedded over Stand-Alone Flash Memory......Page 405
9.3.1 Applications by Device Type......Page 406
9.3.2 Applications by Function......Page 408
9.3.3 Applications by End Product......Page 409
9.3.4 Applications by Usage......Page 411
9.4.1 Special Requirements and Considerations......Page 412
9.4.2 Cell Selection for Embedded Applications......Page 414
9.5.1 Special Requirements and Consideration......Page 423
9.5.2 Flash Module Design for Embedded Applications......Page 425
9.5.3 Design Techniques for Embedded Flash Module......Page 427
References......Page 432
10.1 Introduction......Page 436
10.2 SiO(2) as Tunnel Dielectric—Historical Perspective......Page 437
10.3 Early Work on Silicon Nitride as a Tunnel Dielectric......Page 438
10.4 Jet-Vapor Deposition Silicon Nitride Deposition......Page 439
10.5 Properties of Gate-Quality JVD Silicon Nitride Films......Page 440
10.6 Deposited Silicon Nitride as Tunnel Dielectric......Page 446
10.7 N-Channel Floating-Gate Device with Deposited Silicon Nitride Tunnel Dielectric......Page 454
10.8 P-Channel Floating-Gate Device with Deposited Silicon Nitride Tunnel Dielectric......Page 458
10.10 Tunnel Dielectric for SONOS Cell......Page 461
10.11 Prospects for High-K Dielectrics......Page 463
10.12.1 Crested Barrier......Page 466
10.12.2 U-Shaped Barrier......Page 468
References......Page 469
11.1 Introduction......Page 474
11.2.1 Overview of Cycling-Induced Degradations......Page 476
11.2.2 Channel Hot-Electron Programming-Induced Oxide Degradation......Page 478
11.2.3 Tunnel-Erase-Induced Oxide Degradation......Page 485
11.2.4 Erratic Erase......Page 491
11.3 Flash Memory Data Retention......Page 495
11.3.1 Activation Energy and Accelerated Data Retention Bake Tests......Page 496
11.3.2 Charge-Loss and Gain Mechanisms in EPROMs and Flash EPROMs......Page 502
11.3.3 Flash EEPROM Cycling-Induced Data Retention Issues......Page 506
11.3.4 Data Retention Characteristics Related to Tunnel Oxide and Floating-Gate Poly Texture......Page 510
11.3.5 Soft Errors......Page 513
11.4.1 Read Disturb and the Effects of Cycling......Page 516
11.4.2 Program Disturb......Page 520
11.4.4 Block-to-Block Disturbs......Page 524
11.5 Stress-Induced Tunnel Oxide Leakage Current......Page 525
11.5.1 Uniform SILC in Thin Oxide......Page 526
11.5.2 SILC in Thin Oxide after Bipolarity Stress......Page 531
11.5.3 Microscopic Characteristics of Stress-Induced Leakage Current (mSILC)......Page 537
11.5.4 Stress-Induced Leakage Current in Oxynitride......Page 539
11.5.5 Stress-Induced Leakage Current as the Limiting Factor for Tunnel Oxide Scaling......Page 540
11.6.1 Poly-to-Poly Erase and Its Reliability Issues......Page 541
11.6.2 Source-Side Injection and Its Reliability Issues......Page 546
11.7 Process Impacts on Flash Memory Reliability......Page 554
11.7.2 Effects of Floating-Gate Process and Morphology......Page 555
11.7.3 Stacked Gate SAS (Self-Aligned Source) Etch Process and Erase Distribution......Page 557
11.7.4 In-Line Plasma Charging Damage......Page 559
11.7.5 Impacts of Intermetal Dielectric and Passivation Films on Flash Memory Reliability......Page 562
11.8.1 High-Voltage Transistor Technology......Page 565
11.8.2 Reliability of HV Transistors in Flash Memory Products......Page 566
11.8.3 Process Defects: The Role of Cycling and Burn-in......Page 568
11.9 Design and System Impacts on Flash Memory Reliability......Page 572
11.9.1 Embedded Erase and Program Algorithm......Page 573
11.9.2 Redundancy and Defect Mapping......Page 576
11.9.3 Error Correction Concepts and Techniques......Page 577
11.10.1 Introduction to Reliability Testing and Screening......Page 581
11.10.2 Classification of Flash Memory Reliability Tests......Page 583
11.10.3 Acceleration Models of the Reliability Tests......Page 586
11.10.4 Flash Memory Sort and Reliability Test Flow......Page 588
11.10.5 Flash Memory Product Qualification Flow......Page 590
11.10.6 Burn-In and Reliability Monitoring Program......Page 593
11.10.7 Failure Rate Calculations......Page 594
11.11.2 Erratic Erase......Page 599
11.11.3 Stress-Induced-Leakage-Current Related Retention Effects......Page 600
11.11.4 Detrapping-Related Retention Effects......Page 601
11.11.5 Qualification Methods......Page 602
11.11.6 Flash Memory Floating-Gate to Floating-Gate Coupling......Page 603
11.11.7 New Program Disturb Phenomenon in NAND Flash Memory......Page 604
11.11.8 Impacts of Random Telegraph Signals and Few-Electron Phenomena on the Scaling of Flash Memories......Page 605
References......Page 608
12.1 Introduction......Page 620
12.2 Pursuit of Low-Cost Memory......Page 621
12.3.1 Intel StrataFlash Technology......Page 623
12.3.3 Multilevel Cell Concept......Page 625
12.4.2 Flash Cell Structure and Operation......Page 628
12.4.3 Multilevel Cell Operation......Page 632
12.4.4 Mixed Signal Design Implementation......Page 637
12.5 Low-Cost Design Implementation......Page 640
12.7 Standard Product Feature Set......Page 641
12.7.4 Reliability......Page 642
References......Page 643
13.1 Introduction......Page 646
13.2.2 Programming Voltage......Page 648
13.2.5 Scaling......Page 652
13.3 NROM Memories......Page 653
13.3.2 Memory Cell and Array; Structure and Operation......Page 654
13.3.3 Storage Mechanism......Page 661
13.3.4 Reliability......Page 667
13.3.5 Quad NROM Technology......Page 674
13.3.6 Fabrication......Page 679
13.3.7 Scaling......Page 681
13.3.8 Products......Page 684
13.4.1 Introduction......Page 687
13.4.2 Storage Mechanism......Page 689
13.4.3 Memory Cells and Arrays......Page 693
13.4.4 Fabrication......Page 699
13.4.5 Nonvolatile Characteristics......Page 700
13.4.6 Scaling......Page 702
13.4.7 Reliability......Page 703
13.4.8 Die and Test Cost......Page 704
13.4.9 Ferroelectric Products......Page 705
13.4.10 Ferroelectric Memory Summary......Page 706
13.5.1 Introduction......Page 707
13.5.2 Magnetic Random-Access Memory with Giant Magnetoresistive Devices......Page 708
13.5.3 Magnetic Random-Access Memory with Magnetic Tunnel Junction Devices......Page 713
13.5.4 Programming Characteristics......Page 714
13.5.5 Fabrication......Page 715
13.5.7 Scaling......Page 716
13.5.9 Die and Test Cost......Page 717
13.6.2 Electric Charge Quantization in Solids......Page 718
13.6.3 Single-Electron Effects in Memory Cells......Page 720
13.6.5 Few-Electron Memories......Page 722
13.7.1 Introduction......Page 725
13.7.2 Programmable Diode Technologies......Page 727
13.7.3 Hybrid CMOS/Nanodevice Resistive Memories......Page 729
13.7.4 Expected Performance......Page 730
13.8.2 Crested Tunnel Barriers......Page 732
13.8.3 NOVORAM/FGRAM Cell and Architecture......Page 735
13.9.1 Introduction......Page 736
13.9.3 GST Phase Change Material......Page 738
13.9.4 Memory Cell......Page 741
13.9.5 Memory Array and Support Circuitry......Page 749
13.9.6 Fabrication......Page 750
13.9.7 Scaling......Page 751
13.9.8 Reliability......Page 754
13.9.9 Products......Page 756
References......Page 757
Index......Page 770
About the Editors......Page 788