Nios II Processor Reference Handbook

Nios II Processor Reference Handbook......Page 1
Contents......Page 3
Chapter Revision Dates......Page 5
Section I. Nios II Processor Design......Page 7
Nios II Processor System Basics......Page 9
Getting Started with the Nios II Processor......Page 10
Customizing Nios II Processor Designs......Page 11
Standard Peripherals......Page 12
Automated System Generation......Page 13
Document Revision History......Page 14
2. Processor Architecture......Page 17
Processor Implementation......Page 18
Register File......Page 19
Custom Instructions......Page 20
Floating-Point Instructions......Page 21
Software Development Considerations......Page 22
Exception Controller......Page 24
Internal Interrupt Controller......Page 25
Memory and I/O Organization......Page 26
Instruction and Data Buses......Page 27
Data Master Port......Page 28
Effective Use of Cache Memory......Page 29
Tightly-Coupled Memory......Page 30
Memory Management Unit......Page 31
Memory Protection Unit......Page 32
JTAG Debug Module......Page 33
Hardware Triggers......Page 34
Triggering on Ranges of Values......Page 35
Execution vs. Data Trace......Page 36
Document Revision History......Page 37
Operating Modes......Page 39
User Mode......Page 40
Virtual Addressing......Page 41
Virtual Memory Address Space......Page 42
Physical Memory Address Space......Page 43
TLB Organization......Page 44
TLB Lookups......Page 45
Memory Regions......Page 46
Access Permissions......Page 47
General-purpose Registers......Page 48
Control Registers......Page 49
The status Register......Page 50
The estatus Register......Page 52
The cpuid Register......Page 53
The pteaddr Register......Page 54
The tlbacc Register......Page 55
The tlbmisc Register......Page 56
The badaddr Register......Page 58
The config Register......Page 59
The mpubase Register......Page 60
The mpuacc Register......Page 61
Shadow Register Sets......Page 64
The sstatus Register......Page 65
MPU Region Read and Write Operations......Page 67
Terminology......Page 68
Exception Overview......Page 69
Reset Exceptions......Page 71
Break Exceptions......Page 72
Interrupt Exceptions......Page 73
External Interrupt Controller Interface......Page 74
Internal Interrupt Controller......Page 76
Unimplemented Instruction......Page 77
Supervisor-Only Data Address......Page 78
Division Error......Page 79
TLB Permission Violation......Page 80
Exception Processing Flow......Page 81
Exception Flow with the EIC Interface......Page 82
Exception Flow with the Internal Interrupt Controller......Page 83
Exceptions and Processor Status......Page 84
With Extra Exception Information......Page 85
Handling Nested Exceptions......Page 86
Nested Exceptions with an External Interrupt Controller......Page 87
Returning From Interrupt and Instruction-Related Exceptions......Page 89
Masking Interrupts with an External Interrupt Controller......Page 90
Cache Memory......Page 91
Virtual Address Aliasing......Page 92
Data Transfer Instructions......Page 93
Move Instructions......Page 94
Shift and Rotate Instructions......Page 95
Program Control Instructions......Page 96
No-Operation Instruction......Page 97
Document Revision History......Page 98
Core Nios II Tab......Page 101
Multiply and Divide Settings......Page 102
Reset Vector......Page 103
Fast TLB Miss Exception Vector......Page 104
Memory Protection Unit Settings......Page 105
Instruction Master Settings......Page 106
Data Master Settings......Page 107
Advanced Features Tab......Page 108
Exception Checking......Page 109
HardCopy Compatibility......Page 111
MMU......Page 112
JTAG Debug Module Tab......Page 113
Debug Level Settings......Page 114
Break Vector......Page 115
Custom Instruction Tab......Page 116
Floating-Point Hardware Custom Instruction......Page 117
Endian Converter Custom Instruction......Page 118
Interrupt Vector Custom Instruction......Page 119
The Quartus II IP File......Page 120
Document Revision History......Page 121
Section II. Nios II Processor Implementation and Reference......Page 123
5. Nios II Core Implementation Details......Page 125
Device Family Support......Page 127
Overview......Page 128
Multiply and Divide Performance......Page 129
Memory Access......Page 130
Instruction and Data Caches......Page 131
Tightly-Coupled Memory......Page 133
Execution Pipeline......Page 134
Instruction Performance......Page 135
Exception Handling......Page 136
External Interrupt Controller Interface......Page 137
Overview......Page 138
Multiply and Divide Performance......Page 139
Instruction Cache......Page 140
Execution Pipeline......Page 141
Instruction Performance......Page 142
Overview......Page 143
Instruction Performance......Page 144
Document Revision History......Page 145
Nios II Versions......Page 147
Architecture Revisions......Page 148
Nios II/f Core......Page 149
Nios II/s Core......Page 151
Nios II/e Core......Page 152
JTAG Debug Module Revisions......Page 153
Document Revision History......Page 154
Data Types......Page 155
Register Usage......Page 156
Stacks......Page 157
Further Examples of Stacks......Page 158
Stack Frame for a Function with Variable Arguments......Page 159
Function Prologues......Page 160
Arguments and Return Values......Page 161
Return Values......Page 162
Relocation......Page 163
ABI for Linux Systems......Page 165
Linux Toolchain Relocation Information......Page 166
Thread-Local Storage......Page 167
Linux Operating System Call Interface......Page 169
Linux Process Initialization......Page 170
Linux Position-Independent Code......Page 171
Function Addresses......Page 172
Procedure Linkage Table......Page 173
Linux Program Interpreter......Page 174
Development Environment......Page 175
Document Revision History......Page 176
R-Type......Page 177
J-Type......Page 178
Instruction Opcodes......Page 179
Assembler Pseudo-Instructions......Page 180
Instruction Set Reference......Page 181
add add......Page 183
addi add immediate......Page 184
and bitwise logical and......Page 185
andhi bitwise logical and immediate into high halfword......Page 186
andi bitwise logical and immediate......Page 187
beq branch if equal......Page 188
bge branch if greater than or equal signed......Page 189
bgeu branch if greater than or equal unsigned......Page 190
bgt branch if greater than signed......Page 191
bgtu branch if greater than unsigned......Page 192
ble branch if less than or equal signed......Page 193
bleu branch if less than or equal to unsigned......Page 194
blt branch if less than signed......Page 195
bltu branch if less than unsigned......Page 196
bne branch if not equal......Page 197
br unconditional branch......Page 198
break debugging breakpoint......Page 199
bret breakpoint return......Page 200
call call subroutine......Page 201
callr call subroutine in register......Page 202
cmpeq compare equal......Page 203
cmpeqi compare equal immediate......Page 204
cmpge compare greater than or equal signed......Page 205
cmpgei compare greater than or equal signed immediate......Page 206
cmpgeu compare greater than or equal unsigned......Page 207
cmpgeui compare greater than or equal unsigned immediate......Page 208
cmpgt compare greater than signed......Page 209
cmpgti compare greater than signed immediate......Page 210
cmpgtu compare greater than unsigned......Page 211
cmpgtui compare greater than unsigned immediate......Page 212
cmple compare less than or equal signed......Page 213
cmplei compare less than or equal signed immediate......Page 214
cmpleu compare less than or equal unsigned......Page 215
cmpleui compare less than or equal unsigned immediate......Page 216
cmplt compare less than signed......Page 217
cmplti compare less than signed immediate......Page 218
cmpltu compare less than unsigned......Page 219
cmpltui compare less than unsigned immediate......Page 220
cmpne compare not equal......Page 221
cmpnei compare not equal immediate......Page 222
custom custom instruction......Page 223
div divide......Page 224
divu divide unsigned......Page 225
eret exception return......Page 226
flushd flush data cache line......Page 227
flushda flush data cache address......Page 228
flushi flush instruction cache line......Page 229
flushp flush pipeline......Page 230
initd initialize data cache line......Page 231
initda initialize data cache address......Page 232
initi initialize instruction cache line......Page 233
jmp computed jump......Page 234
jmpi jump immediate......Page 235
ldb / ldbio load byte from memory or I/O peripheral......Page 236
ldbu / ldbuio load unsigned byte from memory or I/O peripheral......Page 237
ldh / ldhio load halfword from memory or I/O peripheral......Page 238
ldhu / ldhuio load unsigned halfword from memory or I/O peripheral......Page 239
ldw / ldwio load 32-bit word from memory or I/O peripheral......Page 240
mov move register to register......Page 241
movhi move immediate into high halfword......Page 242
movi move signed immediate into word......Page 243
movia move immediate address into word......Page 244
movui move unsigned immediate into word......Page 245
mul multiply......Page 246
muli multiply immediate......Page 247
mulxss multiply extended signed/signed......Page 248
mulxsu multiply extended signed/unsigned......Page 249
mulxuu multiply extended unsigned/unsigned......Page 250
nextpc get address of following instruction......Page 251
nop no operation......Page 252
nor bitwise logical nor......Page 253
or bitwise logical or......Page 254
orhi bitwise logical or immediate into high halfword......Page 255
ori bitwise logical or immediate......Page 256
rdctl read from control register......Page 257
rdprs read from previous register set......Page 258
ret return from subroutine......Page 259
rol rotate left......Page 260
roli rotate left immediate......Page 261
ror rotate right......Page 262
sll shift left logical......Page 263
slli shift left logical immediate......Page 264
sra shift right arithmetic......Page 265
srai shift right arithmetic immediate......Page 266
srl shift right logical......Page 267
srli shift right logical immediate......Page 268
stb / stbio store byte to memory or I/O peripheral......Page 269
sth / sthio store halfword to memory or I/O peripheral......Page 270
stw / stwio store word to memory or I/O peripheral......Page 271
sub subtract......Page 272
subi subtract immediate......Page 273
sync memory synchronization......Page 274
trap trap......Page 275
wrctl write to control register......Page 276
wrprs write to previous register set......Page 277
xor bitwise logical exclusive or......Page 278
xorhi bitwise logical exclusive or immediate into high halfword......Page 279
Document Revision History......Page 280
How to Contact Altera......Page 283
Typographic Conventions......Page 284