Nano Interconnects: Device Physics, Modeling and Simulation

Cover
Half Title
Title Page
Copyright Page
Contents
List of Figures
List of Tables
Preface
Acknowledgments
About the Authors
1. Prefatory Concepts and More
	1.1 Introduction
		1.1.1 Prolegomenon to Material for Interconnects Designs
		1.1.2 Prolegomenon to Interconnects Repeater Buffer Design
	1.2 Epoch of On-Chip Interconnects
		1.2.1 Introduction
		1.2.2 Background and Evolution of Interconnect Technology
		1.2.3 Review of Adopted Design Methodology for Interconnect Modeling
		1.2.4 Need for Repeater Insertion
		1.2.5 Performance Tuning of On-Chip Interconnects on the Basis of Design Metrics
	1.3 Summary
	1.4 Motivation
	1.5 Book Outline
	References
2. Interconnect Modeling
	2.1 Introduction
	2.2 Types of Interconnects on a Chip
	2.3 Interconnect Models: Constraints and Requirements
	2.4 Interconnect Material Challenges and Tactical Elucidation
		2.4.1 Limitations of Conventional (Al/Cu) Interconnect Technology
		2.4.2 State-of-the-Art Emerging Interconnect Technology
			a Optical Interconnect
			b Spintronic Switches-Based Interconnect
			c Graphene-Based (CNT and GNR) Interconnect
			Behavior of Electrons in Empty Space
			Behavior of Electrons in a Finite Empty Solid
			Behavior of Electrons in a Periodic Solid: Kronig-Penney Model
			Bravais Lattice
			Primitive Vectors
			Primitive Unit Cell
			Reciprocal Lattice
			Band Structure of Graphene
			Band Structure of CNTs from Graphene
			Band Structure of Zigzag CNTs and the Derivation of the Bandgap
			2.4.2.1 Dominion of CNT Interconnect
			The CNT Lattice
			The Methods for CNT Synthesis
			Arc Discharge Method
			Laser Ablation Method
			Chemical Vapor Deposition Method
			The Methods for CNT Purification
			Gas Phase Purification Technique
			Liquid Phase Purification Technique
			Intercalation Purification Technique
			The Attributes of CNTs
			a Electrical Resistivity
			b Strength and Elasticity
			c Thermal Resistivity and Expansion
			d Aspect Ratio
			e Absorbent
			2.4.2.2 Dominion of GNR Interconnect
			Basic Structure of GNRs
			The Methods for GNR Synthesis
	2.5 Electrical Impedance Modeling of On-Chip Interconnects
		2.5.1 Geometry of Conventional Copper Interconnect and Impedance Calculation
			2.5.1.1 Interconnect Resistance Estimation
			Diffusion Barrier
			Surface and Grain Boundary Scattering
			Temperature Effect
			2.5.1.2 Interconnect Capacitance Estimation
			2.5.1.3 Interconnect Inductance Estimation
			High-Frequency Effects: Skin Effect
		2.5.2 Geometry of CNT Interconnect and Impedance Calculation
			Equivalent RLC Model of CNT Interconnect
			Single-Walled CNT (SWCNT) Interconnect
			Resistance of Isolated SWCNT
			Capacitance of Isolated SWCNT
			Inductance of Isolated SWCNT
			Multi-Walled CNT (MWCNT) Interconnect
			MTL and ESC Models of MWCNT Interconnects
			Resistance of Individual Shell of MWCNT
			Inductance of Individual Shell of MWCNT
			Capacitance of Individual Shell of MWCNT
			SWCNT Bundle Interconnect
			Resistance of SWCNT Bundle interconnect
			Inductance of SWCNT Bundle interconnect
			Capacitance of SWCNT Bundle Interconnect
		2.5.3 Geometry of GNR Interconnect and Impedance Calculation
			Resistance of MLGNR interconnect
			Inductance of MLGNR Interconnect
			Capacitance of MLGNR Interconnect
			Interconnect Technology and Impedance Parameters
			Thermal Stability Analysis of Copper and CNT Interconnects
	2.6 Summary
	EXERCISES
		Multiple-Choice Questions
		Short-Answer Questions
		Long-Answer Questions
	Answers to Multiple-Choice Questions
	References
3. Repeater Buffer Modeling
	3.1 Background
	3.2 Need of Repeater Insertion Technique
	3.3 Design Criteria of Repeater Insertion
	3.4 Modeling of Repeater Buffer for On-Chip Interconnects
		3.4.1 Limitation of Conventional (CMOS) Buffer Fabrication Technology
		3.4.2 State-of-the-Art Emerging Buffer Fabrication Technology
		3.4.2 (a) State-of-the-Art Emerging (Nanowire Transistors) Buffer Fabrication Technology
		3.4.2 (b) State-of-the-Art Emerging (Quantum-Dot Cellular Automata) Fabrication Technology
		3.4.2 (c) State-of-the-Art Emerging (CNTFET) Buffer Fabrication Technology
			Carbon Nanotube
			Carbon Nanotube Field-Effect Transistor
			CNTFET Construction and Device Geometry
			CNTFET Operation and Working
			Current Transport in CNTFET
			Analysis of 1D Ballistic Carbon Nanotube Field-Effect Transistor
		3.4.2 (d) State-of-the-Art Emerging (GNRFET) Buffer Fabrication Technology
			Graphene Nanoribbon
			Armchair Graphene Nanoribbon
			Zigzag Graphene Nanoribbon
			Process Technology Used for Fabrication of Graphene
			Properties of Graphene
			Structural Properties of Graphene
			Electronic Properties of Graphene
			Thermal Properties of Graphene
			Graphene Nanoribbon Field-Effect Transistor
			Types of Graphene Nanoribbon Field-Effect Transistor
			Metal Oxide Semiconductor Type (MOS-GNRFET)
			Schottky Barrier Type (SB-GNRFET)
			Doped Channel GNRFET
			Lightly Doped Drain and Source (LDDS GNRFET)
			Single Gate (SG-GNRFET)
			Double Gate (DG-GNRFET)
			Asymmetric Gate (AG-GNRFET)
			Electrically Activated Source Extension (ESE-GNRFET)
			Dual Material Gate (DMG-GNRFET)
			Two Different Gate Insulator (TDI-GNRFET)
			Extra Peak Electric Field (EPF-GNRFET)
	3.5 Performance Analysis of State-of-the-Art DSM BUFFERS
		3.5.1 Delay Analysis
			Buffer Delay Estimation
			Interconnect Wire Delay Estimation
			RC Delay Model
			Elmore Delay Model
		3.5.2 Power Analysis
			Power Dissipation Components of Repeater Inserted Interconnect Network
			Dynamic Power
			Short Circuit Power
			Leakage Power in Buffer
			Power Reduction Techniques
		3.5.3 Electro Thermal Stability Analysis
	3.6 Architecture and Working of Repeater Buffer for On-Chip Interconnects
		Basic NOT Logic Gate as Repeater
		LECTOR as Repeater
		Schmitt-Trigger as Repeater
		Current Mode Logic (CML) Buffer as Repeater
	3.7 Cross-Technology Performance Benchmarking of Repeater Buffer for On-Chip Nano Interconnects
	3.8 Summary
	Exercises
		Multiple-Choice Questions
		Short-Answer Questions
		Long-Answer Questions
	Answers to Multiple-Choice Questions Chapter 3
	References
4. Signal Integrity Analysis
	4.1 Introduction
	4.2 Signal Integrity: A Challenge in Interconnect Modeling
	4.3 Crosstalk Mechanism
		Inductive Crosstalk
		Electrostatic Crosstalk
		Effect of Crosstalk Glitch
		Factors on Which Height of Crosstalk Depends
	4.4 Crosstalk Analysis
		Prolegomenon to FDTD Technique
			4.4.1 FDTD Model for Crosstalk Analysis of FET-Driven Coupled Copper Interconnects
			Assimilation of Near End and Far End Boundary Conditions
			a Near-End Boundary Condition
			b Far-End Boundary Condition
		4.4.2 FDTD Model for Crosstalk Analysis of Carbon Nanotube (CNT) Interconnects
			Assimilation of Near-End Boundary Conditions
		4.4.3 FDTD Model for Crosstalk Analysis of Graphene Nanoribbon (GNR) Interconnects
	4.5 Crosstalk Result Analysis and Discussions
	4.6 Summary
	Exercises
		Multiple-Choice Questions
		Short-Answer Questions
		Long-Answer Questions
	Answers to Multiple-Choice Questions
	References
Index