Multicore Processors and Systems

cover-large.jpg......Page 1
Integrated Circuits and Systems......Page 2
Preface......Page 5
Multicore Design Considerations......Page 6
Programming for Multicores......Page 8
Case Studies......Page 9
Current and Future Directions......Page 12
Acknowledgments......Page 13
Contents......Page 14
Contributors......Page 15
1.1 Introduction......Page 17
1.1.1 The End of Monolithic Processors......Page 18
1.1.2 Tiled Multicore Architectures......Page 19
1.1.3 Raw: A Prototype Tiled Multicore Processor......Page 21
1.1.4 Chapter Overview......Page 23
1.2 Raw Architecture Overview......Page 0
1.2.1 On-Chip Networks......Page 24
1.2.3 ISA Analogs to Physical Resources......Page 26
1.3 Raw Chip Implementation......Page 27
1.4 Results......Page 28
1.4.1 Experimental Methodology......Page 29
1.4.2 ILP Computation......Page 31
1.4.3 Stream Computation......Page 33
1.4.3.1 StreamIt......Page 34
1.4.3.2 Hand-Optimized Stream Applications......Page 35
1.4.4 Server......Page 37
1.4.5 Bit-Level Computation......Page 38
1.5 Analysis......Page 40
1.6 Related Architectures......Page 43
1.7 Conclusion......Page 45
References......Page 46
2.1 Introduction......Page 50
2.2 Interconnect Fundamentals......Page 51
2.2.1 Interfacing an On-Chip Network to a Multicore System......Page 52
2.2.2 Topology......Page 53
2.2.3 Routing......Page 54
2.2.4 Flow Control......Page 57
2.2.5 Router Microarchitecture......Page 59
2.3 Case Studies......Page 63
2.4.1 TRIPS Overview......Page 65
2.4.2 Operand Network Architecture......Page 67
2.4.3 OPN/Processor Integration......Page 68
2.4.4 Area and Timing......Page 70
2.5 Intel TeraFLOPS Chip......Page 72
2.5.2 Packet Format, Routing, and Flow Control......Page 74
2.5.3 Router Microarchitecture......Page 75
2.5.5 Double-Pumped Crossbar......Page 77
2.5.6 Mesochronous Communication......Page 78
2.5.7 Fine-Grain Power Management......Page 79
2.5.8 Experimental Results......Page 80
2.6 Conclusions......Page 81
2.6.3 Overarching Multi-core Chip Architectures......Page 82
References......Page 83
3  Composable Multicore Chips......Page 87
3.1 Introduction......Page 88
3.1.1 Heterogeneous Processors......Page 89
3.1.2 Composable Processors......Page 90
3.2 ISAs for Scalable and Multigranular Systems......Page 92
3.2.1 TRIPS Blocks......Page 93
3.2.2 Direct Instruction Communication......Page 94
3.2.3 Composable Architectures......Page 95
3.3.1 TRIPS Tiled Microarchitecture......Page 96
3.3.2 TRIPS Tiles......Page 99
3.3.3.1 Block Fetch Protocol......Page 102
3.3.3.2 Distributed Execution......Page 103
3.3.3.3 Block/Pipeline Flush Protocol......Page 104
3.3.3.4 Block Commit Protocol......Page 105
3.3.4 Discussion......Page 106
3.4 Composable Lightweight Processor Architectures......Page 107
3.4.1 Overview of TFlex Operation......Page 109
3.4.2 Composable Instruction Fetch......Page 110
3.4.3 Composable Control-Flow Prediction......Page 111
3.4.4 Composable Instruction Execution......Page 112
3.4.6 Composable Instruction Commit......Page 114
3.5 Experimental Evaluation......Page 115
3.5.1 Serial Programs......Page 116
3.5.2 Multitasking Workloads......Page 117
3.5.3 Composability Overheads and Benefits......Page 119
3.6 Summary......Page 120
References......Page 121
4.1 Introduction......Page 124
4.2.1 Where is the Parallelism?......Page 126
4.2.2 Goals......Page 127
4.2.3 Putting Things Together......Page 128
4.3 High-Level Execution Model......Page 130
4.3.1 Organization and Hardware--Software Split......Page 134
4.4.1 Performance Factors......Page 136
4.4.2 Task Selection......Page 138
4.4.3 Control Flow......Page 141
4.4.4 Register Values......Page 142
4.4.5 Memory Values......Page 146
4.4.5.1 Address Resolution Buffer (ARB)......Page 147
4.4.5.2 Speculative Versioning Cache (SVC)......Page 148
4.4.5.3 Memory Dependence Prediction and Synchronization......Page 151
4.5 Performance, Complexity, and Scalability......Page 152
4.7 Concluding Remarks......Page 154
References......Page 155
5  Optimizing Memory Transactions for Multicore Systems......Page 157
5.1 Introduction......Page 158
5.2.1 Language Support for Transactions......Page 159
5.2.2 Scalability of Transactional Memory......Page 160
5.2.3 Composing Software Using Transactions......Page 161
5.2.4 Transaction Semantics......Page 162
5.3 Implementing TM in a Multicore Environment......Page 163
5.4.1 Compiling Transactions......Page 165
5.4.2 Runtime Data Structures......Page 167
5.5 Optimizing Software Transactional Memory......Page 168
5.5.1 Optimization Opportunities......Page 169
5.5.3 Compiler Optimizations......Page 170
5.5.3.1 Representing Barrier Operations......Page 171
5.5.3.2 Code Generation Optimizations......Page 173
5.6.1 Hardware-Accelerated STM......Page 174
5.6.2 Hardware-Based Transactional Memory......Page 177
5.6.3 Hybrid Hardware--Software Techniques......Page 180
5.7 Conclusion......Page 181
References......Page 182
6.1 Motivating Trends and History......Page 185
6.2.1 Power......Page 188
6.2.2.1 Operating System......Page 190
6.2.2.2 Hypervisor......Page 191
6.2.3 Application Software and Workloads......Page 192
6.2.4.1 Caches......Page 194
6.2.4.3 Memory-Level Parallelism......Page 196
6.2.4.5 Memory Bandwidth Demands......Page 198
6.2.4.6 Processor Interface......Page 199
6.3.1 First-Generation Single-Core AMD Opteron Chips......Page 200
6.3.1.1 AMD Opteron Processor Core Microarchitecture......Page 201
6.3.2 Second- and Third-Generation AMD Opteron Microarchitecture......Page 207
6.3.2.1 Virtualization......Page 208
6.3.2.2 Power Management......Page 209
6.3.2.3 Cache Hierarchy......Page 210
6.3.2.4 Infrastructure and System Topologies......Page 211
6.4 Conclusions......Page 213
References......Page 214
7.1 Introduction......Page 216
7.2 Building a CMP to Maximize Server Throughput......Page 217
7.2.1 The Simple Core Advantage......Page 218
7.2.2 Keeping the Processors Utilized......Page 219
7.3 The Niagara Server CMP......Page 221
7.3.1 Multithreading on Niagara......Page 222
7.3.2 Memory Resources on Niagara......Page 225
7.3.3 Comparing Niagara with a CMP Using Conventional Cores......Page 228
7.3.4 Niagara Performance Analysis and Limits......Page 229
7.4 The Niagara 2 Server CMP......Page 231
7.4.1 Niagara 2 Core Details......Page 232
7.4.3 Niagara 2 Instruction Execution......Page 233
7.4.4 Niagara 2 Memory Subsystem......Page 234
7.4.5 Niagara 2 Physical Design......Page 235
7.4.6 Niagara 2 Performance Analysis......Page 236
7.5 Simple-Core Limitations......Page 238
7.6 Conclusions......Page 239
References......Page 240
8.1 Principles of Stream Processors......Page 242
8.2 Stream Programming Model......Page 245
8.3 Stream Processor Architecture......Page 248
8.3.1 Execution Overview and Hierarchical Control......Page 249
8.3.2 Locality and the Bandwidth Hierarchy......Page 251
8.3.3.1 Arithmetic Clusters......Page 252
8.4.1 StreamC/KernelC......Page 254
8.4.2 Brook......Page 255
8.4.3 Sequoia......Page 256
8.5.1 The Imagine Stream Processor......Page 257
8.5.1.1 Imagine Processor Architecture......Page 258
8.5.1.2 Analysis......Page 259
8.5.1.3 Summary......Page 261
8.5.2.1 SPI Storm 1 Processor Architecture......Page 262
8.5.3 The Merrimac Streaming Supercomputer......Page 264
8.5.3.1 Merrimac Processor Architecture......Page 266
8.5.3.2 Application Analysis......Page 268
8.6 Scalability of Stream Architectures......Page 271
8.6.1 VLSI Scaling......Page 272
8.6.2 Performance Scaling......Page 274
8.6.3 Summary......Page 276
8.7 Conclusions......Page 277
References......Page 278
9.1 Motivation......Page 282
9.2 Cell Broadband Engine Architecture......Page 285
9.2.2 Memory Flow Control......Page 286
9.2.3 SIMD-RISC Core Architecture......Page 289
9.2.5 Optional Extensions to the Power Architecture......Page 290
9.3 Cell Broadband Engine Micro-Architectureand Implementation......Page 291
9.4.1 The Cell Broadband Engine as a CMP......Page 294
9.4.2 Multi-core Programming Abstractions......Page 296
9.5 Performance of the Cell Broadband Engine Processor......Page 299
9.5.1 Scientific Math Kernel Performance......Page 300
9.5.2 Sorting, Searching, and Graph Algorithms......Page 301
9.5.4 Sample Applications......Page 302
9.6 Summary and Conclusions......Page 303
References......Page 304
Index......Page 307