Modern Semiconductor Devices for Integrated Circuits

Cover......Page 1
1.1 Silicon Crystal Structure......Page 2
1.2 Bond Model of Electrons and Holes......Page 5
1.3.1 Energy Band Diagram......Page 9
1.3.2 Donors and Acceptors in the Band Model......Page 11
1.4 Semiconductors, Insulators, and Conductors......Page 12
1.5.1 Effective Mass......Page 13
1.5.2 How to Measure the Effective Mass......Page 15
1.6 Density of States......Page 16
1.7.1 An Analogy for Thermal Equilibrium......Page 17
1.7.2 Fermi Function—The Probability of an Energy StateBeing Occupied by an Electron......Page 18
1.8.1 Derivation of n and p from D(E) and f(E)......Page 20
1.8.2 Fermi Level and the Carrier Concentrations......Page 22
1.8.3 The np Product and the Intrinsic Carrier Concentration......Page 24
1.9 General Theory of n and p......Page 26
1.10 Carrier Concentrations at Extremely High and Low Temperatures......Page 29
1.11 Chapter Summary......Page 30
Problems......Page 31
References......Page 34
2.1 Thermal Motion......Page 36
2.2.1 Electron and Hole Mobilities......Page 39
2.2.2 Mechanisms of Carrier Scattering......Page 41
2.3 Diffusion Current......Page 47
2.4 Relation Between the Energy Diagram and V, E......Page 48
2.5 Einstein Relationship Between D and μ......Page 49
2.6 Electron–Hole Recombination......Page 51
2.8 Quasi-Equilibrium and Quasi-Fermi Levels......Page 53
2.9 Chapter Summary......Page 55
Problems......Page 57
References......Page 59
3. Device Fabrication Technology......Page 60
3.1 Introduction to Device Frbrication......Page 61
3.2 Oxidation of Silicon......Page 62
3.3 Lithography......Page 65
3.3.1 Wet Lithography......Page 67
3.4 Pattern Transfer—Etching......Page 69
3.5.1 Ion Implantation......Page 71
3.5.3 Solid-Source Diffusion......Page 73
3.6 Dopant Diffusion......Page 74
3.7 Thin-Film Deposition......Page 76
3.7.1 Sputtering......Page 77
3.7.2 Chemical Vapor Deposition (CVD)......Page 78
3.7.3 Epitaxy......Page 79
3.8 Interconnect—The Back-End Process......Page 81
3.9 Testing, Assembly, and Qualification......Page 83
3.10 Chapter Summary - A Device Fabrication Example......Page 84
Problems......Page 86
References......Page 88
Part I: PN Jnction......Page 90
4.1.1 Energy Band Diagram and Depletion Layer of a PN Junction......Page 91
4.1.2 Built-In Potential......Page 92
4.1.3 Poisson’s Equation......Page 94
4.2.1 Field and Potential in the Depletion Layer......Page 95
4.2.2 Depletion-Layer Width......Page 97
4.3 Reverse-Biased PN Junction......Page 98
4.4 Capacitance-Voltage Characteristics......Page 99
4.5 Junction Breakdown......Page 101
4.5.2 Tunneling Breakdown......Page 102
4.5.3 Avalanche Breakdown......Page 103
4.6 Carrier Injection under Forward Bias—Quasi-Equilibrium Boundary Condition......Page 106
4.7 Current Continuity Equation......Page 108
4.8 Excess Carriers in Forward - Biased PN Junction......Page 110
4.9 PN Diode IV Characteristics......Page 113
4.9.1 Contributions from the Depletion Region......Page 115
4.10 Charge Storage......Page 116
4.11 Small-Signal Model of the Diode......Page 117
4.12.1 Solar Cell Basics......Page 118
4.12.2 Light Penetration Depth—Direct-Gap and Indirect-GapSemiconductors......Page 120
4.12.3 Short-Circuit Current and Open-Circuit Voltage......Page 122
4.12.4 Output Power......Page 124
4.13.1 LED Materials and Structures......Page 125
4.13.2 Solid-State Lighting......Page 128
4.14.1 Light Amplification......Page 129
4.14.2 Optical Feedback......Page 132
4.14.3 Diode Laser Applications......Page 133
4.16 Schottky Barriers......Page 134
4.17 Thermionic Emission theory......Page 138
4.18 Schottky Diodes......Page 139
4.19 Applications of Schottky Diodes......Page 141
4.20 Quantum mechanical Tunneling......Page 142
4.21 Ohmic Contacts......Page 143
Part I: PN Junction......Page 146
Part II: Applicattion to Optoelectronic Devices......Page 148
Problems......Page 149
References......Page 157
5. MOS Capacitor......Page 158
5.1 Flat-Band Condition and Flat-Band Voltage......Page 159
5.2 Surface Accumulation......Page 161
5.3 Surface Depletion......Page 162
5.4 Threshold Condition and Threshold Voltage......Page 163
5.5 Strong Inversion beyond Threshold......Page 165
5.5.1 Choice of V_t and Gate Doping Type......Page 166
5.6 MOS C–V Characteristics......Page 169
5.7 Oxide Charge—A Modification to V_fb and V_t......Page 173
5.8 Poly-Si Gate Depletion—Effective Increase in T_OX......Page 175
5.9 Inversion and Accumulation Charge-Layer Thicknesses and Quantum Mechanical Effect......Page 177
5.10.1 CCD Imager......Page 180
5.10.2 CMOS Imager......Page 183
5.11 Chapter Summary......Page 185
Problems......Page 187
References......Page 194
6.1 Introduction to the MOSFET......Page 196
6.2 Complementary MOS (COMS) Technology......Page 199
6.3 Surface Mobilities and High-Mobility FETs......Page 201
6.3.1 Surface Mobilities......Page 202
6.3.2 GaAs MESFET......Page 205
6.3.3 HEMT......Page 206
6.3.4 JFET......Page 207
6.4 MOSFET V_t, Body Effect, and Steep Retrograde Doping......Page 208
6.5 Q_INV in MOSFET......Page 210
6.6 Basic MOSFET IV Model......Page 211
6.7.1 Voltage Transfer Curve (VTC)......Page 215
6.7.2 Inverter Speed—The Importance of I_on......Page 217
6.7.3 Power Consumption......Page 219
6.8 Velocity Saturation......Page 220
6.9 MOSFET IV Model with Velocity Saturation......Page 221
6.10 Parasitic Source–Drain Resistance......Page 226
6.11 Extraction of the Series Resistance and the Effective Channel Length......Page 227
6.12 Velocity Overshoot and Source Velocity Limit......Page 229
6.13 Output Conductance......Page 230
6.14 High-Frequency Performance......Page 231
6.15 MOSFET Noises......Page 233
6.15.2 MOSFET Thermal Noise......Page 234
6.15.3 MOSFET Flicker Noise......Page 236
6.15.4 Signal to Noise Ratio, Noise Factor, Noise Figure......Page 237
6.16.1 SRAM......Page 239
6.16.2 DRAM......Page 241
6.16.3 Nonvolatile (Flash) Memory......Page 243
6.17 Chapter Summary......Page 246
Problems......Page 248
References......Page 257
7.1 Technology Scaling—For Cost, Speed, and Power Consumption......Page 260
7.1.2 Strained Silicon and Other Innovations......Page 262
7.2 Subthreshold Current—“Off” Is Not Totally “Off”......Page 264
7.3 V_t Roll-Off—Short-Channel MOSFETs Leak More......Page 267
7.4 Reducing Gate-Insulator Electrical Thickness 
and Tunneling Leakage 
......Page 271
7.5 How to Reduce W_dep......Page 273
7.6.1 MOSFET with Metal Source/Drain......Page 275
7.7 Trade-Off Between I_on and I_off and Design for Manufacturing......Page 277
7.8 Ultra-Thin-Body SOI and Multigate MOSFETs......Page 278
7.8.1 Ultra-Thin-Body MOSFET and SOI......Page 279
7.8.2 FinFET - Multigate MOSFET......Page 281
7.9 Output Conductance......Page 283
7.10 Device and Process Simulation......Page 284
7.11 MOSFET Compact Model for Circuit Simulation......Page 285
7.12 Chapter Summary......Page 286
Problems......Page 287
References......Page 289
8.1 Introduction to the BJT......Page 292
8.2 Collector Current......Page 294
8.2.1 High-Level Injection Effect......Page 297
8.3 Base Current......Page 298
8.4 Current Gain......Page 299
8.4.2 Narrow Band-Gap Base and Heterojunction BJT......Page 300
8.4.4 Gummel Plot and βF Fall-Off at High and Low IC......Page 301
8.5 Base-Width Modulation by Collector Voltage......Page 303
8.6 Ebers–Moll MODEL......Page 305
8.7.1 Base Charge Storage and Base Transit Time......Page 307
8.7.2 Drift Transistor−Built-In Base Field......Page 308
8.7.3 Emitter-to-Collector Transit Time and Kirk Effect......Page 309
8.8 Small-Signal Model......Page 311
8.9 Cutoff Frequency......Page 313
8.10 Charge Control Model......Page 315
8.11 Model for Large-Signal Circuit Simulation......Page 317
8.12 Chapter Summary......Page 319
Problems......Page 320
References......Page 324
Appendix I......Page 326
Appendix II......Page 330
Appendix III......Page 334
Answers to Selected Problems......Page 338
Index......Page 342
Unit Conversion......Page 353