Modern Computer Architecture and Organization

Cover
Title Page
Copyright and Credits
About Packt
Contributors
Table of Contents
Preface
Section 1: Fundamentals of Computer Architecture
Chapter 1: Introducing Computer Architecture
	The evolution of automated computing devices
		Charles Babbage's Analytical Engine
		ENIAC
		IBM PC
		The iPhone
	Moore's law
	Computer architecture
		Binary and hexadecimal numbers
		The 6502 microprocessor
		The 6502 instruction set
	Summary
	Exercises
Chapter 2: Digital Logic
	Electrical circuits
	The transistor
	Logic gates
	Latches
	Flip-flops
	Registers
	Adders
		Propagation delay
	Clocking
	Sequential logic
	Hardware description languages
		VHDL
	Summary
	Exercises
Chapter 3: Processor Elements
	A simple processor
		Control unit
		Arithmetic logic unit
		Registers
	The instruction set
	Addressing modes
		Immediate addressing mode
		Absolute addressing mode
		Absolute indexed addressing mode
		Indirect indexed addressing mode
	Instruction categories
		Memory load and store instructions
		Register-to-register data transfer instructions
		Stack instructions
		Arithmetic instructions
		Logical instructions
		Branching instructions
		Subroutine call and return instructions
		Processor flag instructions
		Interrupt-related instructions
		No operation instruction
	Interrupt processing
		IRQ processing
		NMI processing
		BRK instruction processing
	Input/output operations
		Programmed I/O
		Interrupt-driven I/O
		Direct memory access
	Summary
	Exercises
Chapter 4: Computer System Components
	Technical requirements
	Memory subsystem
	Introducing the MOSFET
	Constructing DRAM circuits with MOSFETs
		The capacitor
		The DRAM bit cell
		DDR4 SDRAM
		Graphics DDR
		Prefetching
	I/O subsystem
		Parallel and serial data buses
		PCI Express
		SATA
		M.2
		USB
		Thunderbolt
	Graphics displays
		VGA
		DVI
		HDMI
		DisplayPort
	Network interface
		Ethernet
		Wi-Fi
	Keyboard and mouse
		Keyboard
		Mouse
	Modern computer system specifications
	Summary
	Exercises
Chapter 5: Hardware-Software Interface
	Device drivers
		The parallel port
		PCIe device drivers
		Device driver structure
	BIOS
		UEFI
	The boot process
		BIOS boot
		UEFI boot
		Embedded devices
	Operating systems
	Processes and threads
		Scheduling algorithms and process priority
	Multiprocessing
	Summary
	Exercises
Chapter 6: Specialized Computing Domains
	Real-time computing
		Real-time operating systems
	Digital signal processing
		ADCs and DACs
		DSP hardware features
		Signal processing algorithms
	GPU processing
		GPUs as data processors
	Examples of specialized architectures
	Summary
	Exercises
Section 2: Processor Architectures and Instruction Sets
Chapter 7: Processor and Memory Architectures
	Technical Requirements
	The von Neumann, Harvard, and modified Harvard architectures
		The von Neumann architecture
		The Harvard architecture
		The modified Harvard architecture
	Physical and virtual memory
	Paged virtual memory
		Page status bits
		Memory pools
	Memory management unit
	Summary
	Exercises
Chapter 8: Performance-Enhancing Techniques
	Cache memory
		Multilevel processor caches
		Static RAM
		Level 1 cache
		Direct-mapped cache
		Set associative cache
		Fully associative cache
		Processor cache write policies
		Level 2 and level 3 processor caches
	Instruction pipelining
		Superpipelining
		Pipeline hazards
		Micro-operations and register renaming
		Conditional branches
	Simultaneous multithreading
	SIMD processing
	Summary
	Exercises
Chapter 9: Specialized Processor Extensions
	Technical requirements
	Privileged processor modes
		Handling interrupts and exceptions
		Protection rings
		Supervisor mode and user mode
		System calls
	Floating-point mathematics
		The 8087 floating-point coprocessor
		The IEEE 754 floating-point standard
	Power management
		Dynamic voltage frequency scaling
	System security management
	Summary
	Exercises
Chapter 10: Modern Processor Architectures and Instruction Sets
	Technical requirements
	x86 architecture and instruction set
		The x86 register set
		x86 addressing modes
		x86 instruction categories
		x86 instruction formats
		x86 assembly language
	x64 architecture and instruction set
		The x64 register set
		x64 instruction categories and formats
		x64 assembly language
	32-bit ARM architecture and instruction set
		The ARM register set
		ARM addressing modes
		ARM instruction categories
		ARM assembly language
	64-bit ARM architecture and instruction set
		64-bit ARM assembly language
	Summary
	Exercises
Chapter 11: The RISC-V Architecture and Instruction Set
	Technical requirements
	The RISC-V architecture and features
	The RISC-V base instruction set
		Computational instructions
		Control flow instructions
		Memory access instructions
		System instructions
		Pseudo-instructions
		Privilege levels
	RISC-V extensions
		The M extension
		The A extension
		C extension
		The F and D extensions
		Other extensions
	64-bit RISC-V
	Standard RISC-V configurations
	RISC-V assembly language
	Implementing RISC-V in an FPGA
	Summary
	Exercises
Section 3: Applications of Computer Architecture
Chapter 12: Processor Virtualization
	Technical requirements
	Introducing virtualization
		Types of virtualization
		Categories of processor virtualization
	Virtualization challenges
		Unsafe instructions
		Shadow page tables
		Security
	Virtualizing modern processors
		x86 processor virtualization
		ARM processor virtualization
		RISC-V processor virtualization
	Virtualization tools
		VirtualBox
		VMware Workstation
		VMware ESXi
		KVM
		Xen
		QEMU
	Virtualization and cloud computing
	Summary
	Exercises
Domain-Specific Chapter 13: Computer Architectures
	Technical requirements
	Architecting computer systems to meet unique requirements
	Smartphone architecture
		iPhone X
	Personal computer architecture
		Alienware Aurora Ryzen Edition gaming desktop
		Ryzen 9 3950X branch prediction
		Nvidia GeForce RTX 2080 Ti GPU
		Aurora subsystems
	Warehouse-scale computing architecture
		WSC hardware
		Rack-based servers
		Hardware fault management
		Electrical power consumption
		The WSC as a multilevel information cache
	Neural networks and machine learning architectures
		Intel Nervana neural network processor
	Summary
	Exercises
Chapter 14: Future Directions in Computer Architectures
	The ongoing evolution of computer architectures
	Extrapolating from current trends
		Moore's law revisited
		The third dimension
		Increased device specialization
	Potentially disruptive technologies
		Quantum physics
		Spintronics
		Quantum computing
		Carbon nanotubes
	Building a future-tolerant skill set
		Continuous learning
		College education
		Conferences and literature
	Summary
	Exercises
Answers to Exercises
	Chapter 1, Introducing Computer Architecture
	Exercise 1
	Answer
	Exercise 2
	Answer
	Exercise 3
	Answer
	Exercise 4
	Answer
	Exercise 5
	Answer
	Exercise 6
	Answer
	Chapter 2, Digital Logic
	Exercise 1
	Answer
	Exercise 2
	Answer
	Exercise 3
	Answer
	Exercise 4
	Answer
	Exercise 5
	Answer
	Exercise 6
	Answer
	Chapter 3, Processor Elements
	Exercise 1
	Answer
	Exercise 2
	Answer
	Exercise 3
	Answer
	Exercise 4
	Answer
	Exercise 5
	Answer
	Exercise 6
	Answer
	Chapter 4, Computer System Components
	Exercise 1
	Answer
	Exercise 2
	Answer
	Chapter 5, Hardware-Software Interface
	Exercise 1
	Answer
	Exercise 2
	Answer
	Chapter 6, Specialized Computing Domains
	Exercise 1
	Answer
	Exercise 2
	Answer
	Exercise 3
	Answer
	Chapter 7, Processor and Memory Architectures
	Exercise 1
	Answer
	Exercise 2
	Answer
	Exercise 3
	Answer
	Chapter 8, Performance-Enhancing Techniques
	Exercise 1
	Answer
	Exercise 2
	Answer
	Exercise 3
	Answer
	Chapter 9, Specialized Processor Extensions
	Exercise 1
	Answer
	Exercise 2
	Answer
	Exercise 3
	Answer
	Exercise 4
	Answer
	Exercise 5
	Answer
	Exercise 6
	Answer
	Exercise 7
	Answer
	Exercise 8
	Answer
	Chapter 10, Modern Processor Architectures and Instruction Sets
	Exercise 1
	Answer
	Exercise 2
	Answer
	Exercise 3
	Answer
	Exercise 4
	Answer
	Exercise 5
	Answer
	Exercise 6
	Answer
	Exercise 7
	Answer
	Exercise 8
	Answer
	Chapter 11, The RISC-V Architecture and Instruction Set
	Exercise 1
	Answer
	Exercise 2
	Answer
	Exercise 3
	Answer
	Exercise 4
	Answer
	Chapter 12, Processor Virtualization
	Exercise 1
	Answer
	Exercise 2
	Answer
	Exercise 3
	Answer
	Chapter 13, Domain-Specific Computer Architectures
	Exercise 1
	Answer
	Exercise 2
	Answer
	Chapter 14, Future Directions in Computer Architectures
	Exercise 1
	Answer
	Exercise 2
	Answer
	Exercise 3
	Answer
	Exercise 4
	Answer
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