MATLAB Deep Learning HDL Toolbox UG.

What is Deep Learning?
	Introduction to Deep Learning
	Training Process
		Training from Scratch
		Transfer Learning
		Feature Extraction
	Convolutional Neural Networks
Deep Learning Processor
	Deep Learning Processor Architecture
		DDR External Memory
		Generic Convolution Processor
		Activation Normalization
		Conv Controller (Scheduling)
		Generic FC Processor
		FC Controller (Scheduling)
		Deep Learning Processor Applications
Applications and Examples
	MATLAB Controlled Deep Learning Processor
Deep Learning on FPGA Overview
	Deep Learning on FPGA Workflow
	Deep Learning on FPGA Solution and Workflows
		FPGA Advantages
		Deep Learning on FPGA Workflows
Workflow and APIS
	Prototype Deep Learning Networks on FPGA and SoCs Workflow
	Profile Inference Run
	Multiple Frame Support
		Input DDR Format
		Output DDR Format
		Manually Enable Multiple Frame Mode
Fast MATLAB to FPGA Connection Using LIBIIO/Ethernet
	LIBIIO/Ethernet Connection Based Deployment
		Ethernet Interface
		Configure your LIBIIO/Ethernet Connection
		LIBIIO/Ethernet Performance
Networks and Layers
	Supported Networks, Layers, Boards, and Tools
		Supported Pretrained Networks
		Supported Layers
		Supported Boards
		Third-Party Synthesis Tools and Version Support
Custom Processor Configuration Workflow
	Custom Processor Configuration Workflow
	Estimate Performance of Deep Learning Network
		Estimate Performance of Custom Deep Learning Network for Custom Processor Configuration
		Evaluate Performance of Deep Learning Network on Custom Processor Configuration
	Estimate Resource Utilization for Custom Processor Configuration
		Estimate Resource Utilization
		Customize Bitstream Configuration to Meet Resource Use Requirements
	Effects of Custom Deep Learning Processor Parameters on Performance and Resource Utilization
Custom Processor Code Generation Workflow
	Generate Custom Bitstream
		Intel Bitstream Resource Utilization
		Xilinx Bitstream Resource Utilization
	Generate Custom Processor IP
Featured Examples
	Get Started with Deep Learning FPGA Deployment on Intel Arria 10 SoC
	Get Started with Deep Learning FPGA Deployment on Xilinx ZCU102 SoC
	Logo Recognition Network
	Deploy Transfer Learning Network for Lane Detection
	Image Category Classification by Using Deep Learning
	Defect Detection
	Profile Network for Performance Improvement
	Bicyclist and Pedestrian Classification by Using FPGA
	Visualize Activations of a Deep Learning Network by Using LogoNet
	Authoring a Reference Design for Live Camera Integration with Deep Learning Processor IP Core
	Run a Deep Learning Network on FPGA with Live Camera Input
	Running Convolution-Only Networks by using FPGA Deployment
	Accelerate Prototyping Workflow for Large Networks by using Ethernet
	Create Series Network for Quantization
	Vehicle Detection Using YOLO v2 Deployed to FPGA
	Custom Deep Learning Processor Generation to Meet Performance Requirements
	Deploy Quantized Network Example
	Quantize Network for FPGA Deployment
	Evaluate Performance of Deep Learning Network on Custom Processor Configuration
	Customize Bitstream Configuration to Meet Resource Use Requirements
	Vehicle Detection Using DAG Network Based YOLO v2 Deployed to FPGA
	Customize Bitstream Configuration to Meet Resource Use Requirements
	Image Classification Using DAG Network Deployed to FPGA
	Classify Images on an FPGA Using a Quantized DAG Network
	Classify ECG Signals Using DAG Network Deployed To FPGA
Deep Learning Quantization
	Quantization of Deep Neural Networks
		Precision and Range
		Histograms of Dynamic Ranges
	Quantization Workflow Prerequisites
	Calibration
		Workflow
	Validation
		Workflow
	Code Generation and Deployment
Deep Learning Processor IP Core User Guide
	Deep Learning Processor IP Core
	Use Compiler Output for System Integration
		External Memory Address Map
		Compiler Optimizations
		Leg Level Compilations
	External Memory Data Format
		Key Terminology
		Convolution Module External Memory Data Format
		Fully Connected Module External Memory Data Format
	Deep Learning Processor Register Map