Low-Power Processors and Systems on Chips

LOW-POWER PROCESSORS AND SYSTEMS ON CHIPS......Page 2
Preface......Page 4
The Editor......Page 6
Table of Contents......Page 7
Part I: Low-Power Processors and Memories......Page 12
1.1 Introduction......Page 13
1.2.1 Active Power and Delay......Page 14
1.3 Process Selection and Rationale......Page 15
1.3.1 Effective Frequency......Page 16
1.4 Leakage Control via Reverse Body Bias......Page 17
1.4.2 Circuit Configuration......Page 18
1.4.4 Regulator Design......Page 20
1.4.6 Measured Results......Page 22
1.5 System Level Performance......Page 23
1.5.1 System Measurement Results......Page 24
1.6 Process, Voltage, and Temperature Variations......Page 25
1.6.1 Process Variation......Page 26
1.6.3 Temperature Variation......Page 27
1.7.2 Microarchitecture Choice Impact......Page 28
1.8.1 Body Bias Control Techniques......Page 29
1.8.2 Adaptive Body Bias and Supply Bias......Page 31
1.9.1 Clock Generation......Page 32
1.9.2 Experimental Results......Page 34
References......Page 35
2.1 Introduction......Page 37
2.2 The Application Driver......Page 38
2.3.1.1 Memory Architectures......Page 40
2.3.2.1 Memory Architecture......Page 43
2.3.2.3 Datapath Support......Page 44
2.3.3 Turbo Decoding......Page 45
2.3.3.1 Datapath Architecture......Page 46
2.4 DSPs as Part of SoCs......Page 47
2.6 Acknowledgments......Page 49
References......Page 50
3.1 Introduction......Page 52
3.2.1 Problem Definition......Page 53
3.2.2.2 Exploiting the Parallelism......Page 54
3.2.2.3 Reducing the Control Overhead......Page 55
3.3.1 Cluster Architecture......Page 56
3.3.2 RDP Architecture......Page 57
3.3.3.1 SCMD Concept......Page 58
3.3.3.3 Software Reconfiguration......Page 59
3.4 Validation Results......Page 60
3.4.1 Implementation of a WCDMA Receiver......Page 61
3.4.3 Performance Comparisons......Page 62
3.6 Acknowledgments......Page 64
References......Page 65
4.1.1 DSP Architectures Evolution......Page 67
4.1.2 Parallelism, Instruction Coding, Scheduling, and Execution......Page 68
4.1.3 High Performance for Low-Power Systems......Page 69
4.1.4 DSP Performance and Reconfigurability......Page 70
4.2.2 Program Sequencing Unit......Page 71
4.2.5 Host and Debug Unit......Page 73
4.2.7 Pipeline......Page 74
4.2.8 Instruction-Set......Page 75
4.3.1 Address Generation Unit Reconfiguration......Page 77
4.3.2 Data Processing Unit Reconfiguration......Page 78
4.4 Performance Results......Page 80
References......Page 83
5.1 Introduction......Page 85
5.2.1 Datapaths......Page 86
5.2.2 Pipelines......Page 87
5.3 Design Methodologies for Low Power......Page 88
5.4.2 MiniMIPS......Page 90
5.4.3 AMULET1, 2, 3......Page 91
5.4.5 Lutonium......Page 92
5.4.6 MICA......Page 93
5.4.7 ASPRO......Page 95
5.5.1 Introduction......Page 96
5.5.2 Principles of Power Reduction with Operating Systems......Page 97
5.5.4.1 Timing Model for Asynchronous Processor Speed Variation......Page 98
5.5.4.1.2 DVS Additional Energy Costs for Synchronous Processors......Page 99
5.5.6.2 Sporadic Task Voltage Scheduling Algorithm......Page 100
5.5.5.3 Periodic Task Voltage Scheduling Algorithm......Page 102
References......Page 103
6.1 Introduction......Page 108
6.2.2 The Transmitter......Page 109
6.2.5 Comparison with a General DSP Processor......Page 110
6.2.6 Classification of Baseband Processors......Page 111
6.3.1 Basic Principles for Low-Power Design......Page 112
6.3.3 Nonprogrammable Low-Power Baseband Processor Architecture......Page 113
6.3.4 Programmable Baseband Processor (PBP) Architectures......Page 114
6.3.5 PBP Design Challenges......Page 117
6.3.6 Decreasing Supply Voltage......Page 118
6.3.8 System-Level Power Management......Page 119
6.4 Case Study One: Variable Data Length and Computing Precision......Page 120
6.5.3 A New Block Interleaver Implementation......Page 121
6.5.5 Power Issues......Page 122
References......Page 123
7.1 Introduction......Page 125
7.2 Leakage Reduction......Page 126
7.3 Noise Margin and Speed Requirements......Page 128
7.4 Locally Switched Source-Body Bias......Page 129
7.5 Results......Page 131
References......Page 132
8.1 Introduction......Page 134
8.2 Cache Organization......Page 136
8.3.1 Miss Rate......Page 137
8.3.6 Leakage......Page 138
8.4.1 Reducing Cache Access Rate......Page 139
8.4.2.1.1 Word-Line Segmentation......Page 140
8.4.2.1.3 Bit-Line Isolation......Page 141
8.4.2.2.2 Way Prediction......Page 142
8.4.2.2.3 Selective Cache Ways......Page 144
8.4.2.2.4 Selective Cache Sets......Page 145
8.4.2.2.6 Reducing Switching Activity of Tag Checks......Page 146
8.4.2.2.7 Data Compression......Page 148
8.4.4 Leakage Energy Reduction......Page 149
References......Page 151
9.1 Introduction......Page 155
9.2 Memory Partitioning......Page 156
9.2.1 Memory Partitioning for Low Energy......Page 157
9.3 Memory Transfer Optimization......Page 159
9.3.1 Code Compression......Page 160
9.3.2 Data Compression......Page 163
9.4 Conclusions......Page 164
References......Page 165
Part II: Low-Power Systems on Chips......Page 167
10.1 Introduction......Page 168
10.2 Hardware Intensity......Page 169
10.3 Architectural Complexity......Page 172
10.4.1 Frequency-Invariant Formulation......Page 174
10.5 Other Power–Performance Metrics......Page 178
10.6 Example: Adding an Execution Bypass......Page 179
10.7 Conclusions......Page 180
References......Page 181
11.1 Introduction......Page 182
11.2 Related Work......Page 183
11.3.2 SoC Architecture Generation......Page 184
11.4.2 OS Library......Page 186
11.4.3.1 Architecture Analyzer......Page 187
11.4.4 Application to Existing OSs......Page 188
11.5 Experiments......Page 189
11.5.2 VDSL Example......Page 190
11.6 Conclusion......Page 193
References......Page 194
12.1 Introduction......Page 195
12.2 Related Work......Page 196
12.3 SW-Controlled Memory Hierarchy Optimization......Page 197
12.3.1 Memory Hierarchy Layer Assignment Techniques......Page 199
12.3.2 Illustration of the MHLA Techniques......Page 200
12.3.4 Relation to Other Steps of the DTSE Design Methodology......Page 201
12.4.1 The QSDPCM Driver......Page 202
12.4.3 The DAB Driver......Page 204
12.5.1 Compiler-Centric Cache Miss Classification......Page 205
12.5.1.3 Block Prefetch Misses......Page 206
12.5.1.7 Data-Layout Conflict Misses......Page 207
12.5.2 Data-Layout Transformations for Conflict Miss Reduction......Page 208
12.5.3 Case Study for Data-Layout Transformations......Page 210
References......Page 211
13.1 Introduction......Page 214
13.2 Micro-Networks: Architectures and Protocols......Page 215
13.2.2 Data Link, Network, and Transport Layers......Page 216
13.2.3 Software Layers......Page 218
13.3.2 Data-Link Layer......Page 219
13.3.3.2 Wormhole Contention-Look-Ahead Algorithm......Page 221
13.3.3.3 Network Power Consumption......Page 222
13.3.3.3.1 Transport Layer......Page 223
13.3.3.5 Interconnect Network Power Consumption......Page 224
13.3.3.5.1 Application and System Layer......Page 225
References......Page 227
14.1.1 Motivation......Page 230
14.1.3.1 Average Power Dissipation......Page 232
14.1.3.3 Integration and Cost......Page 233
14.2.1 Introduction to RF MEMS......Page 234
14.2.2.3 MEMS/CMOS Codesign......Page 235
14.3.2.1 TRF Envelope Detection......Page 236
14.3.3 Super-Regenerative......Page 237
14.4 Transmitters for Ad Hoc Wireless Sensor Networks......Page 238
14.4.2 Two-Step Transmitter......Page 239
14.4.3 Direct-Modulation Transmitter......Page 240
14.5.1 Low-Current RF Amplification......Page 241
14.5.2 Envelope Detector......Page 243
14.5.4 Nonlinear Power Amplifiers......Page 244
14.5.5 On-Chip References and Bias Circuits......Page 247
14.6 System Integration......Page 248
14.8 Acknowledgments......Page 250
References......Page 251
15.1 Introduction......Page 253
15.2 MANET Routing Protocols......Page 254
15.2.2 Reactive (On-Demand) Protocols......Page 255
15.2.3 Hybrid Routing Protocols......Page 256
15.3.1 Minimum Power Routing......Page 257
15.3.2 Battery -Cost Lifetime-Aware Routing......Page 259
15.3.3.2 Geography-Informed Energy Conservation for Ad Hoc Routing......Page 262
15.3.3.3 Topology Maintenance for Energy Efficiency in Ad Hoc Networks (Span)......Page 263
15.3.4.2 Energy-Aware Multicast Routing......Page 264
15.3.4.3 The Neighbor Cost Effect in Multicast Routing......Page 265
15.4.1 Cost Function......Page 267
15.4.3 Route Maintenance......Page 268
15.5.1.1 Lifetime Prediction......Page 269
15.5.2 Route Discovery......Page 271
15.5.3 Route Expiration......Page 272
15.6.2 Simulation Results......Page 273
References......Page 278
16.1.1 Computational Surfaces......Page 280
16.2 Colloidal Computing......Page 283
16.3.1 Driver Application: Beamforming......Page 284
16.5 Simulation Infrastructure......Page 285
16.5.1 Processing Devices......Page 287
16.5.3 Battery Subsystem......Page 290
16.7 Acknowledgments......Page 292
References......Page 293
Part III: Embedded Software......Page 294
17.1 Introduction......Page 295
17.2.1 Experimental Setups for Average and Instantaneous Current......Page 296
17.2.3 Example of Statistically Generated Model for Average Power......Page 298
17.3 Instruction-Level Models for Predicting Instantaneous Power......Page 302
17.4 Emerging Applications of Instantaneous Power Prediction: Security......Page 303
17.4.1 Simple Power Analysis......Page 304
17.4.2 Differential Power Analysis......Page 305
References......Page 307
18.2 Why Compilers?......Page 309
18.3.1 Power vs. Energy......Page 311
18.3.2 Power/Energy vs. Performance......Page 312
18.4.1 Dynamic Voltage and Frequency Scaling......Page 313
18.4.3 Remote Task Mapping......Page 314
References......Page 315
19.1 Introduction......Page 317
19.1.1 Processor Cores in SoC Design......Page 318
19.1.2 SoC Integration and Low-Power Design......Page 319
19.2.1 The Chess/Checkers Retargetable Tool-Suite......Page 320
19.2.2 Architectural Scope......Page 322
19.2.3 Architectural Exploration......Page 323
19.2.4 Power-Conscious Architectural Design......Page 324
19.3.1 General Characteristics......Page 326
19.3.2 Instruction-Set Architecture......Page 328
19.3.3 Micro-Architecture......Page 329
19.4 An Ultra-Low Power DSP for Audio Coding Applications......Page 330
19.4.2 Architecture......Page 331
19.4.3 Low-Power Techniques......Page 333
19.4.4 Results......Page 334
References......Page 335
20.1 Introduction......Page 337
20.2.1 Input Code......Page 338
20.2.2 Loop Fusion......Page 339
20.2.6 Tiling......Page 340
20.2.9 Tiling as a Loop Transformation......Page 341
20.2.11 Implementation and Tests......Page 342
20.2.14 Conclusion......Page 343
20.3 Exploiting Task-Level and Data-Level Parallelism on the Intel IXP1200......Page 344
20.3.2 Performance Modeling and Evaluation......Page 345
20.3.4 Modeling IXP1200 Architecture......Page 346
20.3.6.2 Per-Packet Time Distribution......Page 347
20.3.6.3 Implementation Results......Page 348
20.3.6.4 Exploring the Implementation Space......Page 349
20.4 Advanced Functional Coverification Using SSDE......Page 350
20.4.1 Coverification Using Our System and Software Design Environment (SSDE)......Page 351
20.4.4 Overview of Seamless......Page 352
20.4.5 Overview of Specman Elite......Page 353
20.4.6.2 e-Based Executable Test Plan......Page 354
20.4.8 Manual Tests Development......Page 356
20.4.9 Automatic Test Pattern Generation......Page 357
References......Page 358
The Contributors......Page 9