Logic and Computer Design Fundamentals

Preface......Page 2
Chapter 1. Digital Systems and Information......Page 11
1-1 INFORMATION REPRESENTATION......Page 12
1-2 NUMBER SYSTEMS......Page 21
1-3 ARITHMETIC OPERATIONS......Page 26
1-4 DECIMAL CODES......Page 31
1-5 ALPHANUMERIC CODES......Page 33
1-6 GRAY CODES......Page 36
PROBLEMS......Page 39
2-1 BINARY LOGIC AND GATES......Page 43
2-2 BOOLEAN ALGEBRA......Page 47
2-3 STANDARD FORMS......Page 56
2-4 Two-LEVEL CIRCUIT OPTIMIZATION......Page 62
2-5 MAP MANIPULATION......Page 73
2-6 PRAGMATIC Two-LEVEL OPTIMIZATION......Page 80
2-7 MULTIPLE-LEVEL CIRCUIT OPTIMIZATION......Page 84
2-8 OTHER GATE TYPES......Page 89
2-9 EXCLUSIVE-OR OPERATOR AND GATES......Page 93
2-10 HIGH-IMPEDANCE OUTPUTS......Page 96
REFERENCES......Page 98
PROBLEMS......Page 99
3-1 DESIGN PROCEDURE......Page 105
3-2 BEGINNING HIERARCHICAL DESIGN......Page 112
3-3 TECHNOLOGY MAPPING......Page 115
3-4 VERIFICATION......Page 119
3-5 COMBINATIONAL FUNCTIONAL BLOCKS......Page 121
3-6 RUDIMENTARY LOGIC FUNCTIONS......Page 123
3-7 DECODING......Page 129
3-8 ENCODING......Page 135
3-9 SELECTING......Page 139
3-10 CHAPTER SUMMARY......Page 146
PROBLEMS......Page 148
Chapter 4. Arithmetic Functions and HDLs
......Page 157
4-1 ITERATIVE COMBINATIONAL CIRCUITS......Page 158
4-2 BINARY ADDERS......Page 159
4-3 BINARY SUBTRACTION......Page 163
4-4 BINARY ADDER-SUBTRACTORS......Page 167
4-5 OTHER ARITHMETIC FUNCTIONS......Page 175
4-6 HARDWARE DESCRIPTION LANGUAGES......Page 181
4-7 HDL REPRESENTATIONS-VHDL......Page 184
4-8 HDL REPRESENTATIONS-VERILOG......Page 195
REFERENCES......Page 204
PROBLEMS......Page 205
Chapter 5. Sequential Circuits......Page 215
5-1 SEQUENTIAL CIRCUIT DEFINITIONS......Page 216
5-2 LATCHES......Page 218
5-3 FLIP-FLOPS......Page 223
5-4 SEQUENTIAL CIRCUIT ANALYSIS......Page 230
5-5 SEQUENTIAL CIRCUIT DESIGN......Page 238
5-6 OTHER FLIP-FLOP TYPES......Page 255
5-7 STATE-MACHINE DIAGRAMS AND APPLICATIONS......Page 258
5-8 HDL REPRESENTATION FOR SEQUENTIAL CIRCUITS-VHDL......Page 272
5-9 HDL REPRESENTATION FOR SEQUENTIAL CIRCUITS-VERILOG......Page 280
5-10 CHAPTER SUMMARY......Page 286
REFERENCES......Page 287
PROBLEMS......Page 288
6-1 THE DESIGN SPACE......Page 303
6-2 GATE PROPAGATION DELAY......Page 312
6-3 FLIP-FLOP TIMING......Page 314
6-4 SEQUENTIAL CIRCUIT TIMING......Page 316
6-5 ASYNCHRONOUS INTERACTIONS......Page 318
6-6 SYNCHRONIZATION AND METASTABILITY......Page 320
6-7 SYNCHRONOUS CIRCUIT PITFALLS......Page 326
6-8 PROGRAMMABLE IMPLEMENTATION TECHNOLOGIES......Page 327
REFERENCES......Page 337
PROBLEMS......Page 338
Chapter 7. Registers and Register Transfers......Page 343
7-1 REGISTERS AND LOAD ENABLE......Page 344
7-2 REGISTER TRANSFERS......Page 347
7-3 REGISTER TRANSFER OPERATIONS......Page 349
7-5 MICROOPERATIONS......Page 352
7-6 MICROOPERATIONS ON A SINGLE REGISTER......Page 358
7-7 REGISTER-CELL DESIGN......Page 374
7-8 MULTIPLEXER AND Bus-BASED TRANSFERS FORMULTIPLE REGISTERS......Page 380
7-9 SERIAL TRANSFER AND MICROOPERATIONS......Page 383
7-10 CONTROL OF REGISTER TRANSFERS......Page 386
7-11 HDL REPRESENTATION FOR SHIFT REGISTERS ANDCOUNTERS-VHDL......Page 403
7-12 HDL REPRESENTATION FOR SHIFT REGISTERS ANDCOUNTERS-VERILOG......Page 406
7-13 MICROPROGRAMMED CONTROL......Page 407
PROBLEMS......Page 410
8-1 MEMORY DEFINITIONS......Page 421
8-2 RANDOM-ACCESS MEMORY......Page 422
8-3 SRAM INTEGRATED CIRCUITS......Page 427
8-4 ARRAY OF SRAM ICs......Page 433
8-5 DRAM ICs......Page 437
8-6 DRAM TYPES......Page 443
8-7 ARRA.vs OF DYNAMIC RAM ICs......Page 448
PROBLEMS......Page 449
Chapter 9. Computer Design Basics......Page 451
9-2 DATAPATHS......Page 452
9-3 THE ARITHMETIC/LOGIC UNIT......Page 455
9-4 THE SHIFTER......Page 461
9-5 DATAPATH REPRESENTATION......Page 463
9-6 THE CONTROL WORD......Page 466
9-7 A SIMPLE COMPUTER ARCHITECTURE......Page 472
9-8 SINGLE-CYCLE HARDWIRED CONTROL......Page 479
9-9 MULTIPLE-CYCLE HARDWIRED CONTROL......Page 486
9-10 CHAPTER SUMMARY......Page 497
PROBLEMS......Page 498
10-1 COMPUTER ARCHITECTURE CONCEPTS......Page 505
10-2 OPERAND ADDRESSING......Page 507
10-3 ADDRESSING MODES......Page 514
10-4 INSTRUCTION SET ARCHITECTURES......Page 521
10-5 DATA-TRANSFER INSTRUCTIONS......Page 522
10-6 DATA-MANIPULATION INSTRUCTIONS......Page 526
10-7 FLOATING-POINT COMPUTATIONS......Page 530
10-8 PROGRAM CONTROL INSTRUCTIONS......Page 535
10-9 PROGRAM INTERRUPT......Page 539
10-10 CHAPTER SUMMARY......Page 543
REFERENCES......Page 544
PROBLEMS......Page 545
Chapter 11. RISC and CISC Central Processing Units......Page 551
11-1 PIPELINED DATAPATH......Page 552
11-2 PIPELINED CONTROL......Page 557
11-3 THE REDUCED INSTRUCTION SET COMPUTER......Page 561
11-4 THE COMPLEX INSTRUCTION SET COMPUTER......Page 582
11-5 MORE ON DESIGN......Page 594
11-6 CHAPTER SUMMARY......Page 600
PROBLEMS......Page 601
12-1 COMPUTER 1/0......Page 605
12-2 SAMPLE PERIPHERALS......Page 606
12-3 1/0 INTERFACES......Page 612
12-4 SERIAL COMMUNICATION......Page 619
12-5 MODES OF TRANSFER......Page 625
12-6 PRIORITY INTERRUPT......Page 628
12-7 DIRECT MEMORY ACCESS......Page 632
REFERENCES......Page 636
PROBLEMS......Page 637
13-1 MEMORY HIERARCHY......Page 641
13-2 LOCALITY OF REFERENCE......Page 644
13-3 CACHE MEMORY......Page 646
13-4 VIRTUAL MEMORY......Page 660
13-5 CHAPTER SUMMARY......Page 666
PROBLEMS......Page 667
Index......Page 671