Lectures on Digital Design Principles (River Publishers Electronic Materials, Circuits and Devices)

Cover
Half Title
Series Page
Title Page
Copyright Page
Table of Contents
Preface
Acknowledgement
List of Figures
List of Tables
List of Abbreviations
Chapter 1: Introduction
	1.1: Objectives
		1.1.1: Equation representation
		1.1.2: Hardware platform implementation
		1.1.3: Sequential design
		1.1.4: Datapath components
		1.1.5: Backend lectures
	1.2: Analog vs. Digital
	1.3: Digital Design
		1.3.1: Levels of digital design
		1.3.2: What do digital designers do?
Chapter 2: Numeral Systems and BCD codes
	2.1: Introduction
		2.1.1: Unary numeral systems
		2.1.2: The positional numeral system, or the place-value system
			2.1.2.1: Binary numbers
			2.1.2.2: Hexadecimal numbers
			2.1.2.3: Octal numbers
			2.1.2.4: Converting from decimal to different bases
			2.1.2.5: Converting from one arbitrary base (p) to another arbitrary base (q)
	2.2: Addition and Subtraction in the Positional Numeral System
	2.3: Negative Numbers in Binary
		2.3.1: Signed magnitude
		2.3.2: The 1’s complement
			2.3.2.1: Addition in the 1’s complement
			2.3.2.2: Subtraction in the 1’s complement
		2.3.3: The 2’s complement
			2.3.3.1: Addition in the 2’s complement
			2.3.3.2: Subtraction in the 2’s complement
	2.4: Strings of Bits and Binary-Coded Decimal Representations
		2.4.1: The 8421 BCD code
		2.4.2: The 2421, 631-1, 84-2-1, and Excess-3 BCD codes
		2.4.3: The biquinary code
		2.4.4: The gray code
		2.4.5: BCD summary
	2.5: More on Number Systems
	2.6: Conclusion and Key Points
Chapter 3: Boolean Algebra and Logic Gates
	3.1: Motivation
	3.2: Huntington Postulates
	3.3: Basic Theorems of Boolean Algebra
		3.3.1: Basic postulates with 0 and 1
		3.3.2: Idempotent laws
		3.3.3: The Law of involution
		3.3.4: Complementarity laws
		3.3.5: Commutative laws
		3.3.6: Associative laws
		3.3.7: Distributive laws
		3.3.8: DeMorgan’s laws
	3.4: Duality
		3.4.1: What you should know from duality
	3.5: Logic Gates for Implementation of Boolean Networks
		3.5.1: AND, OR, and NOT
		3.5.2: Implicant gates
		3.5.3: Other logic gates
		3.5.4: Equivalent gates
		3.5.5: Concept of completeness
	3.6: CMOS Gates
	3.7: General Complementary Switching Network
	3.8: Conclusion
	3.9: Key Points
Chapter 4: Timing Diagrams
	4.1: Notion of Timing Delay in a Circuit
	4.2: Definition of Propagation Delay
	4.3: Timing Diagrams of a Gated Logic
	4.4: The Ring Oscillator: Good Use of Delays
	4.5: Glitches and Hazards: Bad Effects Due to Unequal Path Delays
		4.5.1: Correction of the static-1 hazard
	4.6: Conclusion and Key Points
Chapter 5: Combinational Logic Design Techniques: Part I
	5.1: Designing a Digital System from a Problem Statement
		5.1.1: Stairwell lamp problem
		5.1.2: BCD to seven-segment converter
		5.1.3: Event detector
	5.2: Conclusion and Key Points
Chapter 6: Combinational Logic Design Techniques: Part II
	6.1: Majority Gate Design
		6.1.1: SOP implementation
		6.1.2: POS implementation
		6.1.3: Self-duality
	6.2: Why Different Representations: Two-Level Logic Implementation Styles
		6.2.1: SOP representations
		6.2.2: POS representations
		6.2.3: Compatible representations for CMOS design
	6.3: Hardware Description Languages
		6.3.1: Majority gate and stairwell lamp verilog Implementation
		6.3.2: Full adder verilog implementation
		6.3.3: Ripple carry adder
	6.4: Conclusion and Key Points
Chapter 7: Combinational Logic Minimization
	7.1: Representation for Minimization: Summarization
		7.1.1: Intuitive design approach
		7.1.2: Boolean minimization
	7.2: Graphical Method: The Karnaugh Map
	7.3: Three- and Four-Variable Karnaugh Maps for Logic Circuits
	7.4: Minimizing with Four-Variable K-maps
		7.4.1: Formal definitions
		7.4.2: Example 1: detailed illustration of minimization
		7.4.3: Example 2: prime implicant definition reinforcement
		7.4.4: Example 3: dealing with “Don’t cares”
	7.5: Conclusion and Key Points
Chapter 8: Combinational Building Blocks
	8.1: Decoders
		8.1.1: Implementation of larger-bit decoders
		8.1.2: Using decoders to implement boolean functions
			8.1.2.1: Example 1
			8.1.2.2: Example 2
	8.2: Multiplexers
		8.2.1: Implementation of larger-bit multiplexers
		8.2.2: Using multiplexers to implement boolean functions
			8.2.2.1: Example 1
			8.2.2.2: Example 2
	8.3: MSI Building Blocks
		8.3.1: Decoders
			8.3.1.1: The 74139 decoder
			8.3.1.2: The 74138 Decoder
		8.3.2: Tri-state buffers
			8.3.2.1: Application
			8.3.2.2: The 74541 three-state driver
		8.3.3: Encoders
			8.3.3.1: The 74148 priority encoder
			8.3.3.2: Verilog implementation
		8.3.4: Multiplexers
		8.3.5: Parity circuits
		8.3.6: Comparison circuits
			8.3.6.1: Equality
			8.3.6.2: Greater than and less than
			8.3.6.3: The 74682 magnitude comparator IC
	8.4: Conclusion
	8.5: Key Points
Chapter 9: Foundations of Sequential Design: Part I
	9.1: Taxonomy of Sequential Models
		9.1.1: The mealy machine
		9.1.2: The moore machine
	9.2: Flip-Flops
		9.2.1: Operation of flip-flops and their applications
		9.2.2: Classification of flip-flops
			9.2.2.1: S-R flip-flop
				9.2.2.1.1: Characteristic table
				9.2.2.1.2: State diagram
			9.2.2.2: T flip-flop
				9.2.2.2.1: Characteristic table
				9.2.2.2.2: State diagram
			9.2.2.3: J-K flip-flop1
				9.2.2.3.1: Characteristic table
				9.2.2.3.2: State diagram
			9.2.2.4: D flip-flop
	9.3: Conclusion and Key Points
Chapter 10: Foundations of Sequential Design: Part II
	10.1: Gate Implementation of Flip-Flops and Timing Diagrams
		10.1.1: Simple inverters without feedback
		10.1.2: Single inverter with feedback (oscillator)
		10.1.3: Two inverters with feedback (flip-flop)
		10.1.4: S-R latch
			10.1.4.1: S-R latch timing diagram
			10.1.4.2: Problems with the S-R latch
	10.2: Clocked Flip-Flops
		10.2.1: Clocked S-R flip-flop
		10.2.2: Clocked J-K flip-flop
			10.2.2.1: J-K flip-flop timing diagram
			10.2.2.2: Problems with the J-K flip-flop
		10.2.3: Solutions to the race-around problem
			10.2.3.1: Narrowing the clock pulse width
			10.2.3.2: Separating the inputs and outputs of the flip-flop
				10.2.3.2.1: Master-Slave D flip-flop
				10.2.3.2.2: Master-Slave J-K flip-flop
		10.2.4: IEEE symbols and flip-flop types
		10.2.5: Timing analysis of flip-flop problems
			10.2.5.1: Example 1: timing diagram of a J-K flip-flop
			10.2.5.2: Example 2: timing diagram of J-K flip-flops configured as a counter/binary divider
			10.2.5.3: Example 3: Timing diagram of D flip-flops configured as a ring counter
		10.2.6: Effect of the width of the set pulse
		10.2.7: Dealing with metastability and asynchronous inputs
	10.3: Conclusion and Key Point
	10.4: Problems on Flip-Flops
Index
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