Introduction to Mixed-Signal IC Test and Measurement

Front Matter......Page 1
Preface......Page 3
Table of Contents......Page 10
1.1.1 Analog, Digital, or Mixed-Signal?......Page 24
1.1.2 Common Types of Analog and Mixed-Signal Circuits......Page 25
1.1.3 Applications of Mixed-Signal Circuits......Page 26
1.2.1 The CMOS Fabrication Process......Page 28
1.2.2 Real-World Circuits......Page 29
1.2.3 What is a Test Engineer?......Page 31
1.3.1 Test and Packaging......Page 32
1.3.2 Characterization versus Production Testing......Page 33
1.4.1 Automated Test Equipment......Page 34
1.4.3 Handlers......Page 35
1.4.6 Forced-Temperature Systems......Page 36
1.5.1 Concurrent Engineering......Page 37
1.6.2 Accuracy, Repeatability, and Correlation......Page 38
1.6.4 Economics of Production Testing......Page 39
Problems......Page 40
References......Page 41
2.1.1 General-Purpose Testers versus Focused Bench Equipment......Page 42
2.2.1 General-Purpose Multimeters......Page 43
2.2.2 General-Purpose Voltage/Current Sources......Page 45
2.2.3 Precision Voltage References and User Supplies......Page 46
2.2.5 Relay Matrices......Page 47
2.2.6 Relay Control Lines......Page 48
2.3.3 Source Memory......Page 49
2.3.5 Pin Card Electronics......Page 50
2.3.6 Timing and Formatting Electronics......Page 51
2.4.2 Arbitrary Waveform Generators......Page 54
2.4.4 Clocking and Synchronization......Page 55
2.6.1 Source Path......Page 57
2.6.2 Measurement Path......Page 58
2.7.2 Tester Computer......Page 59
Problems......Page 60
3.1.1 Purpose of Continuity Testing......Page 62
3.1.2 Continuity Test Technique......Page 63
3.1.3 Serial versus Parallel Continuity Testing......Page 65
3.2.1 Purpose of Leakage Testing......Page 66
3.3.1 Importance of Supply Current Tests......Page 67
3.3.2 Test Techniques......Page 68
3.4.1 Voltage Regulators......Page 69
3.4.3 Trimmable References......Page 70
3.5.1 Input Impedance......Page 71
3.5.3 Differential Impedance Measurements......Page 74
3.6.1 V_MID and Analog Ground......Page 75
3.6.3 Output Offset Voltage \0嘀开伀Ⰰ伀匀......Page 76
3.6.4 Single-Ended, Differential, and Common-Mode Offsets......Page 77
3.6.5 Input Offset Voltage \0嘀开䤀一Ⰰ伀匀......Page 79
3.7.1 Closed-Loop Gain......Page 80
3.7.2 Open-Loop Gain......Page 82
3.8.1 DC Power Supply Sensitivity......Page 85
3.8.2 DC Power Supply Rejection Ratio......Page 86
3.9.1 CMRR of Op Amps......Page 87
3.9.2 CMRR of Differential Gain Stages......Page 89
3.10.2 Threshold Voltage......Page 91
3.10.3 Hysteresis......Page 92
3.11.1 Binary Searches versus Step Searches......Page 93
3.11.2 Linear Searches......Page 94
3.12.5 I_OSH and I_OSL Short-Circuit Current......Page 98
Problems......Page 99
References......Page 101
4.1.1 Datalogs \0䐀愀琀愀 䰀椀猀琀猀......Page 102
4.1.2 Lot Summaries......Page 103
4.1.3 Wafer Maps......Page 105
4.1.4 Shmoo Plots......Page 106
4.1.5 Histograms......Page 108
4.2.1 Mean \0䄀瘀攀爀愀最攀 and Standard Deviation \0嘀愀爀椀愀渀挀攀......Page 109
4.2.2 Probabilities and Probability Density Functions......Page 111
4.2.3 The Standard Gaussian Cumulative Distribution Function Phi \0稀......Page 114
4.2.4 Verifying Gaussian Behavior: The Kurtosis and Normal Probability Plot......Page 119
4.3.1 The Uniform Probability Distribution......Page 122
4.3.2 The Sinusoidal Probability Distribution......Page 124
4.3.3 The Binomial Probability Distribution......Page 127
4.4 Modeling the Structure of Randomness......Page 129
4.4.1 Modeling a Gaussian Mixture Using the Expectation-Maximization Algorithm......Page 130
4.4.2 Probabilities Associated with a Gaussian Mixture Model......Page 136
4.5 Sums and Differences of Random Variables......Page 139
4.5.1 The Central Limit Theorem......Page 143
Problems......Page 145
References......Page 149
5.1 Yield......Page 150
5.2.1 Accuracy and Precision......Page 152
5.2.3 Random Errors......Page 153
5.2.4 Resolution \0儀甀愀渀琀椀稀愀琀椀漀渀 䔀爀爀漀爀......Page 154
5.2.7 Correlation......Page 155
5.2.7.4 DIB-to-DIB Correlation......Page 156
5.3 A Mathematical Look at Repeatability, Bias, and Accuracy......Page 157
5.4.2 Hardware Calibration......Page 165
5.4.3 Software Calibration......Page 166
5.4.4 System Calibrations and Checkers......Page 168
5.4.5 Focused Instrument Calibrations......Page 169
5.4.6 Focused DIB Circuit Calibrations......Page 172
5.5 Tester Specifications......Page 174
5.6.1 Analog Filtering......Page 176
5.6.2 Averaging......Page 178
5.7 Guardbands......Page 179
5.8 Effects of Measurement Variability on Test Yield......Page 184
5.9 Effects of Reproducibilty and Process Variation on Yield......Page 187
5.10.1 Goals of SPC......Page 190
5.10.2 Six-Sigma Quality......Page 191
5.10.3 Process Capability: C_p, and C_pk......Page 192
5.10.4 Gauge Repeatability and Reproducibility......Page 193
5.11 Summary......Page 194
Problems......Page 195
References......Page 198
6. DAC Testing......Page 199
6.1.1 Principles of DAC and ADC Conversion......Page 200
6.1.2 Data Formats......Page 204
6.1.4 DAC Failure Mechanisms......Page 208
6.2.3 DC Gain, Gain Error, Offset, and Offset Error......Page 209
6.2.5 DC PSS......Page 212
6.3.1 Absolute Error......Page 213
6.3.2 Monotonicity......Page 214
6.3.3 Differential Nonlinearity......Page 215
6.3.4 Integral Nonlinearity......Page 217
6.3.6 Major Carrier Testing......Page 220
6.3.7 Other Selected-Code Techniques......Page 223
6.4.1 Conversion Time \0匀攀琀琀氀椀渀最 吀椀洀攀......Page 224
6.4.2 Overshoot and Undershoot......Page 225
6.4.5 Glitch Energy \0䜀氀椀琀挀栀 䤀洀瀀甀氀猀攀......Page 226
6.4.6 Clock and Data Feedthrough......Page 227
6.5.2 Audio Reconstruction......Page 228
6.5.4 Video Signal Generators......Page 229
Problems......Page 230
References......Page 233
7.1.2 Statistical Behavior of ADCs......Page 234
7.2.1 Edge Code Testing versus Center Code Testing......Page 239
7.2.3 Servo Method......Page 240
7.2.4 Linear Ramp Histogram Method......Page 241
7.2.5 Conversion from Histograms to Code Edge Transfer Curves......Page 243
7.2.6 Accuracy Limitations of Histogram Testing......Page 244
7.2.7 Rising Ramps versus Falling Ramps......Page 246
7.2.8 Sinusoidal Histogram Method......Page 247
7.3.1 DC Gain and Offset......Page 256
7.3.2 INL and DNL......Page 257
7.3.3 Monotonicity and Missing Codes......Page 259
7.4.1 Conversion Time, Recovery Time, and Sampling Frequency......Page 261
7.4.3 Sparkling......Page 263
7.5.3 Data Transmission......Page 264
Problems......Page 265
References......Page 267
8.1.1 Traditional versus DSP-Based Testing of AC Parameters......Page 269
8.2.2 Sampling: Continuous-Time and Discrete-Time Representation......Page 270
8.2.3 Reconstruction......Page 274
8.2.4 The Sampling Theorem and Aliasing......Page 278
8.2.5 Quantization Effects......Page 281
8.2.6 Sampling Jitter......Page 287
8.3.1 Finite and Infinite Sample Sets......Page 294
8.3.2 Coherent Signals and Noncoherent Signals......Page 295
8.3.3 Peak-to-RMS Control in Coherent Multitones......Page 297
8.3.4 Spectral Bin Selection......Page 298
8.4.1 Simultaneous Testing of Multiple Sampling Systems......Page 303
8.4.2 ATE Clock Sources......Page 304
Problems......Page 306
References......Page 308
9.1.1 Reduced Test Time......Page 309
9.2.1 DSP and Array Processing......Page 310
9.2.2 Fourier Analysis of Periodic Signals......Page 311
9.2.3 The Trigonometric Fourier Series......Page 312
9.2.4 The Discrete-Time Fourier Series......Page 315
9.2.5 Complete Frequency Spectrum......Page 325
9.2.6 Time and Frequency Denormalization......Page 328
9.2.7 Complex Form of the DTFS......Page 329
9.3.1 The Discrete Fourier Transform......Page 331
9.3.2 The Fast Fourier Transform......Page 335
9.3.3 Interpreting the FFT Output......Page 336
9.3.4 Windowing......Page 344
9.4.1 Equivalence of Time- and Frequency-Domain Information......Page 356
9.4.2 Parseval\'s Theorem......Page 359
9.4.3 Frequency-Domain Filtering......Page 360
9.4.4 Noise Weighting......Page 361
9.5 Summary......Page 362
Problems......Page 363
References......Page 367
10.1.1 Types of Analog Channels......Page 368
10.2.1 Absolute Voltage Levels......Page 369
10.2.2 Absolute Gain and Gain Error......Page 373
10.2.4 PGA Gain Tests......Page 375
10.2.5 Frequency Response......Page 380
10.3.1 Phase Response......Page 388
10.3.2 Group Delay and Group Delay Distortion......Page 392
10.4.1 Signal-to-Harmonic Distortion......Page 394
10.4.2 Intermodulation Distortion......Page 397
10.4.3 Adjacent Channel and Noise Power Ratio Tests......Page 398
10.5.1 Common-Mode Rejection Ratio......Page 400
10.5.2 Power Supply Rejection and Power Supply Rejection Ratio......Page 402
10.5.3 Channel-to-Channel Crosstalk......Page 404
10.5.4 Clock and Data Feedthrough......Page 407
10.6.2 Idle Channel Noise......Page 408
10.6.3 Signal to Noise, Signal to Noise and Distortion......Page 410
10.7 Summary......Page 413
Problems......Page 414
11.1.1 What are Sampled Channels?......Page 418
11.1.2 Examples of Sampled Channels......Page 419
11.1.3 Types of Sampled Channels......Page 421
11.2.1 DUT Sampling Rate Constraints......Page 423
11.2.2 Digital Signal Source and Capture......Page 424
11.2.3 Simultaneous DAC and ADC Channel Testing......Page 428
11.2.4 Mismatched Fundamental Frequencies......Page 431
11.2.5 Reconstruction Effects in DACs, AWGs, and other Sampled-Data Circuits......Page 435
11.3 Undersampling and Aliasing......Page 439
11.3.1 Reconstructing the High-Frequency Signal from the Aliased Sample Set......Page 441
11.4.1 Signal Creation and Analysis......Page 447
11.4.2 Intrinsic \0儀甀愀渀琀椀稀愀琀椀漀渀 Errors Associated with the DAC Operation......Page 448
11.5.1 Similarity to Analog Channel Tests......Page 451
11.5.2 Absolute Level, Absolute Gain, Gain Error, and Gain Tracking......Page 453
11.5.3 Frequency Response......Page 457
11.5.4 Phase Response \0䄀戀猀漀氀甀琀攀 倀栀愀猀攀 匀栀椀昀琀......Page 460
11.5.6 Signal to Harmonic Distortion and Intermodulation Distortion......Page 461
11.5.7 Crosstalk......Page 462
11.5.10 Signal-to-Noise Ratio and ENOB......Page 463
11.5.11 Idle Channel Noise......Page 464
Problems......Page 465
References......Page 468
12.1 Introduction to RF Testing......Page 469
12.2.1 Wave Definition of Electrical Signals......Page 471
12.2.2 Measures of Electrical Waves......Page 472
12.2.3 Power Definition......Page 475
12.2.4 Crest Factor......Page 479
12.2.5 Power in dBm......Page 482
12.2.6 Power Transfer......Page 483
12.2.6.1 Maximum Power Transfer......Page 484
12.2.7 Conjugate and Reflectionless Matching......Page 487
12.2.8.1 Insertion Loss......Page 488
12.2.8.2 Transducer Loss......Page 489
12.3 Noise......Page 490
12.3.1.1 Thermal Noise......Page 492
12.3.1.3 Flicker Noise......Page 493
12.3.2 Noise Figure......Page 494
12.3.3.1 Fundamentals......Page 497
12.3.3.2 Spectral Density of Phase Fluctuations......Page 498
12.3.3.3 Spectral Density of Frequency Fluctuations......Page 501
12.3.3.5 Jitter and Integrated Phase Noise......Page 502
12.4.1 Principles of S-Parameters of a Two-Port Network......Page 504
12.4.2.1 Voltage Standing Wave Ratio......Page 509
12.4.2.2 Reflection Coefficient......Page 511
12.4.2.3 Return Loss......Page 512
12.4.2.4 Mismatch Loss......Page 513
12.4.2.5 Mismatch Uncertainty......Page 514
12.4.2.6 Reducing Measurement Uncertainty......Page 521
12.4.2.7 Insertion Loss......Page 524
12.5.1.1 Amplitude Modulation......Page 527
12.5.1.2 Frequency Modulation......Page 529
12.5.1.3 Phase Modulation......Page 532
12.5.2 Digital Modulation......Page 534
12.5.2.2 Frequency Shift Keying......Page 535
12.5.2.4 Constellation Diagram......Page 536
12.5.4 Orthogonal Frequency Division Multiplexing......Page 537
12.6 Summary......Page 539
Problems......Page 540
References......Page 542
13. RF Test Methods......Page 544
13.1.1.1 Calorimetric Power Sensor......Page 545
13.1.1.2 Superheterodyne Power Sensor......Page 546
13.1.1.3 Zero-IF with Sampling Power Sensor......Page 547
13.1.2 Gain Measurement......Page 551
13.1.3 Scalar Power Measures versus Time......Page 559
13.1.4 Intermodulation Measurement......Page 561
13.1.5.2 Binary Search Method......Page 566
13.1.5.3 Interpolation Method......Page 567
13.1.5.4 Modulation Method......Page 570
13.2.1 Principles of a Directional Coupler......Page 571
13.2.2 Directional Couplers on an ATE......Page 573
13.3.1 Noise Figure and Noise Factor Definition......Page 574
13.3.2 Noise Measurement Technique with the Y-Factor Method......Page 576
13.3.4 Comparison of the Noise Figure Test Methods......Page 578
13.4 Phase Noise......Page 580
13.4.1 Measuring Phase Noise Using Spectral Analysis......Page 581
13.4.2 PLL-Based Phase Noise Test Method......Page 586
13.4.3 Delay-Line Phase Noise Test Method......Page 588
13.5 Vector Signal Analysis......Page 589
13.5.2 Test of Relative Phase......Page 591
13.5.3 Error Vector Magnitude Test Method......Page 596
13.5.4 Adjacent Channel Power Tests......Page 598
13.5.4.1 Modulated Sources......Page 599
13.5.4.2 Modulation Measurements......Page 600
13.5.6 Bit Error Rate......Page 601
13.6 Summary......Page 603
Problems......Page 604
References......Page 607
14.1 Synchronous and Asynchronous Communications......Page 608
14.2 Time-Domain Attributes of a Clock Signal......Page 610
14.3 Frequency-Domain Attributes of a Clock Signal......Page 615
14.4 Communicating Serially over a Channel......Page 621
14.4.1 Ideal Channel......Page 622
14.4.2 Real Channel Effects......Page 623
14.4.2.1 Noisy Channel......Page 624
14.4.2.2 Dispersive Channel......Page 625
14.4.2.4 Jitter Classifications......Page 628
14.4.3.1 Received Voltage Decision Level, VTH......Page 629
14.4.3.2 Received Zero-Crossing Decision Level, t_TH......Page 632
14.4.3.3 Combined Effect of Varying Received Voltage Level Decision V_TH and Zero-Crossing Decision Level, t_TH......Page 633
14.5 Bit Error Rate Measurement......Page 634
14.5.1 PRBS Test Patterns......Page 640
14.6.1 Amplitude-Based Scan Test......Page 644
14.6.2 Time-Based Scan Test......Page 651
14.6.3 Dual-Dirac Jitter Decomposition Method......Page 653
14.6.3.1 Total Jitter Definition......Page 659
14.6.4 Gaussian Mixture Jitter Decomposition Method......Page 661
14.7.1 Period and Sinusoidal Jitter \0倀䨀⼀匀䨀......Page 667
14.7.2 Data-Dependent Jitter \0䐀䐀䨀......Page 670
14.7.3 Bounded and Uncorrelated Jitter \0䈀唀䨀......Page 672
14.8.1 Jitter Transfer Test......Page 678
14.8.1.1 Coherent Jitter Generation......Page 679
14.8.1.2 Coherent Phase Extraction Using Analytic Signal Representation......Page 682
14.8.1.3 Final Comments......Page 688
14.8.2 Jitter Tolerance Test......Page 689
14.9 Summary......Page 696
Problems......Page 697
References......Page 703
15.1.1 Purpose of a Device Interface Board......Page 704
15.1.2 DIB Configurations......Page 706
15.2.1 Prototype DIBs versus PCB DIBs......Page 707
15.2.2 PCB CAD Tools......Page 708
15.2.3 Multilayer PCBs......Page 709
15.2.4 PCB Materials......Page 710
15.3.2 Trace Resistance......Page 711
15.3.3 Trace Inductance......Page 712
15.3.4 Trace Capacitance......Page 717
15.3.5 Shielding......Page 723
15.3.6 Driven Guards......Page 724
15.4.1.1 Coaxial Line......Page 725
15.4.1.3 Microstrip Line......Page 726
15.4.1.5 Coupled Transmission Lines......Page 727
15.4.2 Transmission Line Discontinuities......Page 728
15.4.3 Lumped- and Distributed-Element Models......Page 729
15.4.4 Transmission Line Termination......Page 733
15.4.5 Parasitic Lumped Elements......Page 737
15.5.1 Introduction to the Smith Chart......Page 738
15.5.2 Impedance Smith Chart......Page 740
15.5.3 Admittance Smith Chart......Page 743
15.5.4 Immitance Smith Chart......Page 744
15.5.5 Impedance Transformation with Discrete Components on Smith Chart......Page 745
15.5.6 Impedance Matching with a Series and Shunt Component Using the Immitance Smith Chart......Page 748
15.6.1 Grounding......Page 751
15.6.2 Power Distribution......Page 752
15.6.3 Power and Ground Planes......Page 753
15.6.4 Ground Loops......Page 755
15.7.1 DUT Sockets and Contactor Assemblies......Page 756
15.7.2 Contact Pads, Pogo Pins, and Socket Pins......Page 757
15.7.3 Electromechanical Relays......Page 759
15.7.4 Socket Pins......Page 761
15.7.5 Resistors......Page 762
15.7.6 Capacitors......Page 764
15.7.7 Inductors and Ferrite Beads......Page 768
15.7.8 Transformers and Power Splitters......Page 771
15.8.2 Instrumentation Amplifiers......Page 772
15.8.3 V_MID Reference Adder......Page 774
15.8.4 Current-to-Voltage and Voltage-to-Current Conversions......Page 775
15.8.5 Power Supply Ripple Circuits......Page 776
15.9.2 Crosstalk......Page 778
15.9.4 Resistive Drops in Circuit Traces......Page 779
15.9.7 Poor DIB Component Placement and PCB Layout......Page 780
Problems......Page 781
References......Page 783
16.1.1 What is DfT?......Page 784
16.1.3 Differences between Digital DfT and Analog DfT......Page 785
16.2.1 Lower Cost of Test......Page 786
16.2.3 Diagnostics and Characterization......Page 788
16.3.1 Scan Basics......Page 789
16.3.2 IEEE Std. 1149.1 Standard Test Access Port and Boundary Scan......Page 790
16.3.3 Full Scan and Partial Scan......Page 793
16.4.1 Pseudorandom BILBO Circuits......Page 794
16.4.2 Memory BIST......Page 796
16.5.1 Partitioning......Page 797
16.5.2 Digital Resets and Presets......Page 798
16.5.3 Device-Driven Timing......Page 799
16.6.1 Mixed-Signal Boundary Scan \0䤀䔀䔀䔀 匀琀搀⸀ ㄀㄀㐀㤀⸀㐀......Page 801
16.6.2 Analog and Mixed-Signal BIST......Page 803
16.7.1 Common Concepts......Page 804
16.7.2 Accessibility of Analog Signals......Page 805
16.7.3 Analog Test Buses, T-Switches, and Bypass Modes......Page 806
16.7.4 Separation of Analog and Digital Blocks......Page 808
16.7.6 Precharging Circuits and AC Coupling Shorts......Page 811
16.7.8 PLL Testability Circuits......Page 813
16.7.9 DAC and ADC Converters......Page 814
16.8.1 RF Loopback Test......Page 815
16.8.2 RF BIT and BIST......Page 816
16.8.3 Correlation-Based Test......Page 818
16.8.3.1 DC-to-RF Correlation......Page 819
16.8.3.2 Analog-to-RF Correlation......Page 820
Problems......Page 821
References......Page 823
Appendix A: Gaussian Cumulative Distribution Function Values Phi \0稀......Page 826
Answers to Problems......Page 827
A......Page 841
B......Page 844
C......Page 845
D......Page 849
E......Page 852
F......Page 854
G......Page 856
H......Page 857
I......Page 858
L......Page 860
M......Page 862
N......Page 864
O......Page 865
P......Page 866
R......Page 870
S......Page 872
T......Page 878
U......Page 880
V......Page 881
W......Page 882
Z......Page 883