Introduction to Logic Circuits & Logic Design with VHDL

Preface
	Written the Way It Is Taught
	Learning Outcomes
	Teaching by Example
	Course Design
	Instructor Resources
	What´s New in the Third Edition
Acknowledgments
Contents
1: Introduction: Analog Versus Digital
	1.1 Differences Between Analog and Digital Systems
		Concept Check
	1.2 Advantages of Digital Systems Over Analog Systems
		Concept Check
2: Number Systems
	2.1 Positional Number Systems
		2.1.1 Generic Structure
		2.1.2 Decimal Number System (Base 10)
		2.1.3 Binary Number System (Base 2)
		2.1.4 Octal Number System (Base 8)
		2.1.5 Hexadecimal Number System (Base 16)
			Concept Check
	2.2 Base Conversion
		2.2.1 Converting to Decimal
			2.2.1.1 Binary to Decimal
			2.2.1.2 Octal to Decimal
			2.2.1.3 Hexadecimal to Decimal
		2.2.2 Converting from Decimal
			2.2.2.1 Decimal to Binary
			2.2.2.2 Decimal to Octal
			2.2.2.3 Decimal to Hexadecimal
		2.2.3 Converting Between 2n Bases
			2.2.3.1 Binary to Octal
			2.2.3.2 Binary to Hexadecimal
			2.2.3.3 Octal to Binary
			2.2.3.4 Hexadecimal to Binary
			2.2.3.5 Octal to Hexadecimal
			2.2.3.6 Hexadecimal to Octal
				Concept Check
	2.3 Binary Arithmetic
		2.3.1 Addition (Carries)
		2.3.2 Subtraction (Borrows)
			Concept Check
	2.4 Unsigned and Signed Numbers
		2.4.1 Unsigned Numbers
		2.4.2 Signed Numbers
			2.4.2.1 Signed Magnitude
			2.4.2.2 One´s Complement
			2.4.2.3 Two´s Complement
			2.4.2.4 Arithmetic with Two´s Complement
				Concept Check
3: Digital Circuitry and Interfacing
	3.1 Basic Gates
		3.1.1 Describing the Operation of a Logic Circuit
			3.1.1.1 The Logic Symbol
			3.1.1.2 The Truth Table
			3.1.1.3 The Logic Function
			3.1.1.4 The Logic Waveform
		3.1.2 The Buffer
		3.1.3 The Inverter
		3.1.4 The AND Gate
		3.1.5 The NAND Gate
		3.1.6 The OR Gate
		3.1.7 The NOR Gate
		3.1.8 The XOR Gate
		3.1.9 The XNOR Gate
			Concept Check
	3.2 Digital Circuit Operation
		3.2.1 Logic Levels
		3.2.2 Output DC Specifications
		3.2.3 Input DC Specifications
		3.2.4 Noise Margins
		3.2.5 Power Supplies
		3.2.6 Switching Characteristics
		3.2.7 Data Sheets
			Concept Check
	3.3 Logic Families
		3.3.1 Complementary Metal Oxide Semiconductors (CMOS)
			3.3.1.1 CMOS Operation
			3.3.1.2 CMOS Inverter
			3.3.1.3 CMOS NAND Gate
			3.3.1.4 CMOS NOR Gate
		3.3.2 Transistor-Transistor Logic (TTL)
			3.3.2.1 TTL Operation
		3.3.3 The 7400 Series Logic Families
			3.3.3.1 Part-Numbering Scheme
			3.3.3.2 DC Operating Conditions
			3.3.3.3 Pin-Out Information for the DIP Packages
				Concept Check
	3.4 Driving Loads
		3.4.1 Driving Other Gates
		3.4.2 Driving Resistive Loads
		3.4.3 Driving LEDs
			Concept Check
4: Combinational Logic Design
	4.1 Boolean Algebra
		4.1.1 Operations
		4.1.2 Axioms
			4.1.2.1 Axiom #1: Logical Values
			4.1.2.2 Axiom #2: Definition of Logical Negation
			4.1.2.3 Axiom #3: Definition of a Logical Product
			4.1.2.4 Axiom #4: Definition of a Logical Sum
			4.1.2.5 Axiom #5: Logical Precedence
		4.1.3 Theorems
			4.1.3.1 DeMorgan´s Theorem of Duality
			4.1.3.2 Identity
			4.1.3.3 Null Element
			4.1.3.4 Idempotent
			4.1.3.5 Complements
			4.1.3.6 Involution
			4.1.3.7 Commutative Property
			4.1.3.8 Associative Property
			4.1.3.9 Distributive Property
			4.1.3.10 Absorption
			4.1.3.11 Uniting
			4.1.3.12 DeMorgan´s Theorem
		4.1.4 Functionally Complete Operation Sets
			Concept Check
	4.2 Combinational Logic Analysis
		4.2.1 Finding the Logic Expression from a Logic Diagram
		4.2.2 Finding the Truth Table from a Logic Diagram
		4.2.3 Timing Analysis of a Combinational Logic Circuit
			Concept Check
	4.3 Combinational Logic Synthesis
		4.3.1 Canonical Sum of Products
		4.3.2 The Minterm List (Σ)
		4.3.3 Canonical Product of Sums (POS)
		4.3.4 The Maxterm List (Π)
		4.3.5 Minterm and Maxterm List Equivalence
			Concept Check
	4.4 Logic Minimization
		4.4.1 Algebraic Minimization
		4.4.2 Minimization Using Karnaugh Maps
			4.4.2.1 Formation of a K-Map
			4.4.2.2 Logic Minimization Using K-Maps (Sum of Products)
			4.4.2.3 Logic Minimization Using K-Maps (Product of Sums)
			4.4.2.4 Minimal Sum
		4.4.3 Don´t Cares
		4.4.4 Using XOR Gates
			Concept Check
	4.5 Timing Hazards and Glitches
		Concept Check
5: VHDL (Part 1)
	5.1 History of Hardware Description Languages
		Concept Check
	5.2 HDL Abstraction
		Concept Check
	5.3 The Modern Digital Design Flow
		Concept Check
	5.4 VHDL Constructs
		5.4.1 Data Types
			5.4.1.1 Enumerated Types
			5.4.1.2 Range Types
			5.4.1.3 Physical Types
			5.4.1.4 Vector Types
			5.4.1.5 User-Defined Enumerated Types
			5.4.1.6 Array Type
			5.4.1.7 Subtypes
		5.4.2 Libraries and Packages
		5.4.3 The Entity
		5.4.4 The Architecture
			5.4.4.1 Signal Declarations
			5.4.4.2 Constant Declarations
			5.4.4.3 Component Declarations
				Concept Check
	5.5 Modeling Concurrent Functionality in VHDL
		5.5.1 VHDL Operators
			5.5.1.1 Assignment Operator
			5.5.1.2 Logical Operators
			5.5.1.3 Numerical Operators
			5.5.1.4 Relational Operators
			5.5.1.5 Shift Operators
			5.5.1.6 Concatenation Operator
		5.5.2 Concurrent Signal Assignments
		5.5.3 Concurrent Signal Assignments with Logical Operators
		5.5.4 Conditional Signal Assignments
		5.5.5 Selected Signal Assignments
		5.5.6 Delayed Signal Assignments
			Concept Check
	5.6 Structural Design Using Components
		5.6.1 Component Instantiation
			5.6.1.1 Explicit Port Mapping
			5.6.1.2 Positional Port Mapping
				Concept Check
	5.7 Overview of Simulation Test Benches
		Concept Check
6: MSI Logic
	6.1 Decoders
		6.1.1 Example: One-Hot Decoder
		6.1.2 Example: 7-Segment Display Decoder
			Concept Check
	6.2 Encoders
		6.2.1 Example: One-Hot Binary Encoder
			Concept Check
	6.3 Multiplexers
		Concept Check
	6.4 Demultiplexers
		Concept Check
7: Sequential Logic Design
	7.1 Sequential Logic Storage Devices
		7.1.1 The Cross-Coupled Inverter Pair
		7.1.2 Metastability
		7.1.3 The SR Latch
		7.1.4 The S′R′ Latch
		7.1.5 SR Latch with Enable
		7.1.6 The D-Latch
		7.1.7 The D-Flip-Flop
			Concept Check
	7.2 Sequential Logic Timing Considerations
		Concept Check
	7.3 Common Circuits Based on Sequential Storage Devices
		7.3.1 Toggle Flop Clock Divider
		7.3.2 Ripple Counter
		7.3.3 Switch Debouncing
		7.3.4 Shift Registers
			Concept Check
	7.4 Finite State Machines
		7.4.1 Describing the Functionality of a FSM
			7.4.1.1 State Diagrams
			7.4.1.2 State Transition Tables
		7.4.2 Logic Synthesis for a FSM
			7.4.2.1 State Memory
			7.4.2.2 Next State Logic
			7.4.2.3 Output Logic
			7.4.2.4 The Final Logic Diagram
		7.4.3 FSM Design Process Overview
		7.4.4 FSM Design Examples
			7.4.4.1 Serial Bit Sequence Detector
			7.4.4.2 Vending Machine Controller
				Concept Check
	7.5 Counters
		7.5.1 2-Bit Binary Up Counter
		7.5.2 2-Bit Binary Up/Down Counter
		7.5.3 2-Bit Gray Code Up Counter
		7.5.4 2-Bit Gray Code Up/Down Counter
		7.5.5 3-Bit One-Hot Up Counter
		7.5.6 3-Bit One-Hot Up/Down Counter
			Concept Check
	7.6 Finite State Machine´s Reset Condition
		Concept Check
	7.7 Sequential Logic Analysis
		7.7.1 Finding the State Equations and Output Logic Expressions of a FSM
		7.7.2 Finding the State Transition Table of a FSM
		7.7.3 Finding the State Diagram of a FSM
		7.7.4 Determining the Maximum Clock Frequency of a FSM
			Concept Check
8: VHDL (Part 2)
	8.1 The Process
		8.1.1 Sensitivity List
		8.1.2 The Wait Statement
		8.1.3 Sequential Signal Assignments
		8.1.4 Variables
			Concept Check
	8.2 Conditional Programming Constructs
		8.2.1 If/Then Statements
		8.2.2 Case Statements
		8.2.3 Infinite Loops
		8.2.4 While Loops
		8.2.5 For Loops
			Concept Check
	8.3 Signal Attributes
		Concept Check
	8.4 Test Benches
		8.4.1 Report Statement
		8.4.2 Assert Statement
			Concept Check
	8.5 Packages
		8.5.1 STD_LOGIC_1164
			8.5.1.1 STD_LOGIC Resolution Function
			8.5.1.2 STD_LOGIC_1164 Logical Operators
			8.5.1.3 STD_LOGIC_1164 Edge Detection Functions
			8.5.1.4 STD_LOGIC Type Conversion Functions
		8.5.2 NUMERIC_STD
			8.5.2.1 NUMERIC_STD Arithmetic Functions
			8.5.2.2 NUMERIC_STD Logical Functions
			8.5.2.3 NUMERIC_STD Comparison Functions
			8.5.2.4 NUMERIC_STD Edge Detection Functions
			8.5.2.5 NUMERIC_STD Conversion Functions
			8.5.2.6 NUMERIC_STD Type Casting
		8.5.3 NUMERIC_STD_UNSIGNED
			8.5.3.1 NUMERIC_STD_UNSIGNED Conversion Functions
		8.5.4 NUMERIC_BIT
		8.5.5 NUMERIC_BIT_UNSIGNED
			8.5.5.1 NUMERIC_BIT_UNSIGNED Conversion Functions
		8.5.6 MATH_REAL
		8.5.7 MATH_COMPLEX
		8.5.8 TEXTIO and STD_LOGIC_TEXTIO
			8.5.8.1 Example: Writing to an External File from a Test Bench
			8.5.8.2 Example: Writing to STD_OUTPUT from a Test Bench
			8.5.8.3 Example: Reading from an External File in a Test Bench
			8.5.8.4 Example: Reading Space-Delimited Data from an External File in a Test Bench
		8.5.9 Legacy Packages (STD_LOGIC_ARITH/UNSIGNED/SIGNED)
			Concept Check
9: Behavioral Modeling of Sequential Logic
	9.1 Modeling Sequential Storage Devices in VHDL
		9.1.1 D-Latch
		9.1.2 D-Flip-Flop
		9.1.3 D-Flip-Flop with Asynchronous Reset
		9.1.4 D-Flip-Flop with Asynchronous Reset and Preset
		9.1.5 D-Flip-Flop with Synchronous Enable
			Concept Check
	9.2 Modeling Finite State Machines in VHDL
		9.2.1 Modeling the States with User-Defined, Enumerated Data Types
		9.2.2 The State Memory Process
		9.2.3 The Next State Logic Process
		9.2.4 The Output Logic Process
		9.2.5 Explicitly Defining State Codes with Subtypes
			Concept Check
	9.3 FSM Design Examples in VHDL
		9.3.1 Serial Bit Sequence Detector in VHDL
		9.3.2 Vending Machine Controller in VHDL
		9.3.3 2-Bit, Binary Up/Down Counter in VHDL
			Concept Check
	9.4 Modeling Counters in VHDL
		9.4.1 Counters in VHDL Using the Type UNSIGNED
		9.4.2 Counters in VHDL Using the Type INTEGER
		9.4.3 Counters in VHDL Using the Type STD_LOGIC_VECTOR
		9.4.4 Counters with Enables in VHDL
		9.4.5 Counters with Loads
			Concept Check
	9.5 RTL Modeling
		9.5.1 Modeling Registers in VHDL
		9.5.2 Shift Registers in VHDL
		9.5.3 Registers as Agents on a Data Bus
			Concept Check
10: Memory
	10.1 Memory Architecture and Terminology
		10.1.1 Memory Map Model
		10.1.2 Volatile Versus Nonvolatile Memory
		10.1.3 Read-Only Versus Read/Write Memory
		10.1.4 Random Access Versus Sequential Access
			Concept Check
	10.2 Nonvolatile Memory Technology
		10.2.1 ROM Architecture
		10.2.2 Mask Read-Only Memory (MROM)
		10.2.3 Programmable Read-Only Memory (PROM)
		10.2.4 Erasable Programmable Read-Only Memory (EPROM)
		10.2.5 Electrically Erasable Programmable Read-Only Memory (EEPROM)
		10.2.6 FLASH Memory
			Concept Check
	10.3 Volatile Memory Technology
		10.3.1 Static Random Access Memory (SRAM)
		10.3.2 Dynamic Random Access Memory (DRAM)
			Concept Check
	10.4 Modeling Memory with VHDL
		10.4.1 Read-Only Memory in VHDL
		10.4.2 Read/Write Memory in VHDL
			Concept Check
11: Programmable Logic
	11.1 Programmable Arrays
		11.1.1 Programmable Logic Array (PLA)
		11.1.2 Programmable Array Logic (PAL)
		11.1.3 Generic Array Logic (GAL)
		11.1.4 Hard Array Logic (HAL)
		11.1.5 Complex Programmable Logic Devices (CPLDs)
			Concept Check
	11.2 Field Programmable Gate Arrays (FPGAs)
		11.2.1 Configurable Logic Block (or Logic Element)
		11.2.2 Look-Up Tables (LUTs)
		11.2.3 Programmable Interconnect Points (PIPs)
		11.2.4 Input/Output Blocks (IOBs)
		11.2.5 Configuration Memory
			Concept Check
12: Arithmetic Circuits
	12.1 Addition
		12.1.1 Half Adders
		12.1.2 Full Adders
		12.1.3 Ripple Carry Adder (RCA)
		12.1.4 Carry Look-Ahead Adder (CLA)
		12.1.5 Adders in VHDL
			12.1.5.1 Structural Model of a Ripple Carry Adder in VHDL
			12.1.5.2 Structural Model of a Carry Look-Ahead Adder in VHDL
			12.1.5.3 Behavior Model of an Adder Using UNSIGNED Data Types
				Concept Check
	12.2 Subtraction
		Concept Check
	12.3 Multiplication
		12.3.1 Unsigned Multiplication
		12.3.2 A Simple Circuit to Multiply by Powers of Two
		12.3.3 Signed Multiplication
			Concept Check
	12.4 Division
		12.4.1 Unsigned Division
		12.4.2 A Simple Circuit to Divide by Powers of Two
		12.4.3 Signed Division
			Concept Check
13: Computer System Design
	13.1 Computer Hardware
		13.1.1 Program Memory
		13.1.2 Data Memory
		13.1.3 Input/Output Ports
		13.1.4 Central Processing Unit
			13.1.4.1 Control Unit
			13.1.4.2 Data Path: Registers
			13.1.4.3 Data Path: Arithmetic Logic Unit (ALU)
		13.1.5 A Memory Mapped System
			Concept Check
	13.2 Computer Software
		13.2.1 Opcodes and Operands
		13.2.2 Addressing Modes
			13.2.2.1 Immediate Addressing (IMM)
			13.2.2.2 Direct Addressing (DIR)
			13.2.2.3 Inherent Addressing (INH)
			13.2.2.4 Indexed Addressing (IND)
		13.2.3 Classes of Instructions
			13.2.3.1 Loads and Stores
			13.2.3.2 Data Manipulations
			13.2.3.3 Branches
				Concept Check
	13.3 Computer Implementation: An 8-Bit Computer Example
		13.3.1 Top Level Block Diagram
		13.3.2 Instruction Set Design
		13.3.3 Memory System Implementation
			13.3.3.1 Program Memory Implementation in VHDL
			13.3.3.2 Data Memory Implementation in VHDL
			13.3.3.3 Implementation of Output Ports in VHDL
			13.3.3.4 Implementation of Input Ports in VHDL
			13.3.3.5 Memory data_out Bus Implementation in VHDL
		13.3.4 CPU Implementation
			13.3.4.1 Data Path Implementation in VHDL
			13.3.4.2 ALU Implementation in VHDL
			13.3.4.3 Control Unit Implementation in VHDL
				13.3.4.3.1 Detailed Execution of LDA_IMM
				13.3.4.3.2 Detailed Execution of LDA_DIR
				13.3.4.3.3 Detailed Execution of STA_DIR
				13.3.4.3.4 Detailed Execution of ADD_AB
				13.3.4.3.5 Detailed Execution of BRA
				13.3.4.3.6 Detailed Execution of BEQ
					Concept Check
	13.4 Architecture Considerations
		13.4.1 Von Neumann Architecture
		13.4.2 Harvard Architecture
			Concept Check
14: Floating-Point Systems
	14.1 Overview of Floating-Point Numbers
		14.1.1 Limitations of Fixed-Point Numbers
		14.1.2 The Anatomy of a Floating-Point Number
		14.1.3 The IEEE 754 Standard
		14.1.4 Single Precision Floating-Point Representation (32-bit)
		14.1.5 Double Precision Floating-Point Representation (64-bit)
		14.1.6 IEEE 754 Special Values
		14.1.7 IEEE 754 Rounding Types
		14.1.8 Other Capabilities of the IEEE 754 Standard
			Concept Check
	14.2 IEEE 754 Base Conversions
		14.2.1 Converting from Decimal into IEEE 754 Single Precision Numbers
		14.2.2 Converting from IEEE 754 Single Precision Numbers into Decimal
			Concept Check
	14.3 Floating-Point Arithmetic
		14.3.1 Addition and Subtraction of IEEE 754 Numbers
		14.3.2 Multiplication and Division of IEEE 754 Numbers
			Concept Check
	14.4 Floating-Point Modeling in VHDL
		14.4.1 Floating-Point Packages in the IEEE Library
		14.4.2 The IEEE_Proposed Library
			Concept Check
Appendix A: List of Worked Examples
Appendix B: Concept Check Solutions
Index