Integrated Frequency Synthesizers for Wireless Systems

Cover......Page 1
Half-title......Page 3
Title......Page 5
Copyright......Page 6
Contents......Page 7
Preface......Page 9
Acknowledgments......Page 10
1 Local oscillator requirements......Page 11
1.1 AM and PM signals......Page 12
1.2 Effect of phase noise and spurs......Page 16
1.3 Frequency accuracy......Page 19
1.5 References......Page 22
2.1.1 Introduction......Page 24
2.1.2 Simple loop......Page 25
2.1.3 Linear models of the loop-building blocks......Page 28
2.1.4 PLL linear model......Page 30
2.2.1 Integer-N divider PLL......Page 33
2.2.2 Phase frequency detector and charge pump......Page 35
2.2.3 Linear continuous-time analysis of the charge-pump PLL......Page 37
2.3.1 Limit of the continuous-time approximation......Page 42
2.3.2 Limit of the linear approximation......Page 43
2.4.1 Phase noise spectra transfer functions......Page 48
2.4.2 Reference spurs......Page 51
2.4.3 Reference spur magnitude: CP current mismatch......Page 53
2.4.5 Reference spur magnitude: supply disturbance......Page 55
2.5 References......Page 57
3.1 Beyond the integer-N approach......Page 59
3.2.1 Operating principle......Page 60
3.2.2 Control pattern generation and phase error......Page 61
3.2.3 Fractional spurs......Page 64
3.2.4 Fractional-spur compensation......Page 65
3.3.1 Shaping the spur spectrum......Page 68
3.3.2 Quantization noise and oversampling......Page 69
3.3.3 Delta Sigma modulation......Page 70
3.3.4 Frequency divider control by a Delta Sigma modulator......Page 73
3.4.1 Output phase spectrum versus modulator order......Page 75
3.4.2 A Delta Sigma modulator for fractional-N PLL......Page 77
3.4.3 Bandwidth versus reference frequency......Page 78
3.4.4 Dithering the modulator......Page 80
3.4.5 Other fractional-N techniques......Page 81
3.5 References......Page 82
4.2.1 Energy balance......Page 84
4.2.2 The tank Q-factor......Page 86
4.2.3 Barkhausen criterion......Page 88
4.2.4 Start-up and amplitude stability......Page 89
4.2.5 Effect of the transconductor delay......Page 90
4.2.6 Oscillator tuning......Page 91
4.3.1 The Colpitts oscillator......Page 92
4.3.2 The open-loop gain......Page 94
4.3.3 Negative impedance analysis......Page 95
4.3.4 Oscillation amplitude......Page 96
4.4.1 MOSFET cross-coupled oscillators......Page 101
4.4.2 Tail resonator......Page 104
4.4.3 MOSFET complementary cross-coupled oscillator......Page 106
4.4.4 Bipolar cross-coupled oscillators......Page 107
4.5 References......Page 111
5.2 Linear and time-invariant model......Page 113
5.3.1 Figure of merit......Page 115
5.3.2 Limits to the exploitation of noise–power trade-off......Page 116
5.3.3 Technology scaling......Page 117
5.4.1 Time-domain approach: the impulse sensitivity function......Page 118
5.4.2 Frequency-domain approach: the harmonic transfer function......Page 122
5.5.1 Cross-coupled oscillator: tail noise......Page 126
5.5.2 Cross-coupled oscillator: noise of the transistor pair (HTF method)......Page 128
5.5.3 Cross-coupled oscillator: noise of the transistor pair (ISF method)......Page 131
5.5.5 Colpitts oscillator: collector current noise (HTF method)......Page 132
5.5.6 Colpitts oscillator: collector current noise (ISF method)......Page 134
5.7 References......Page 141
6.2.1 On-chip inductors......Page 143
6.2.2 Partial inductance......Page 144
6.2.3 Inductor losses, models and parasitics......Page 148
6.2.4 The inductor quality factor......Page 149
6.3.1 Spiral inductors......Page 151
6.3.2 Microstrip and coplanar waveguide inductors......Page 152
6.4.1 Varactor key performance......Page 156
6.4.2 Diode varactors......Page 157
6.4.3 MOS varactors......Page 159
6.4.4 Tuning range and losses......Page 160
6.5 Switched tuning......Page 163
6.6 References......Page 165
7.2 Tuning curve and sensitivity coefficients......Page 167
7.3 Noise up-conversion from varactors......Page 171
7.4.1 Low tuning sensitivity and automatic frequency control......Page 176
7.4.2 Low-noise automatic amplitude control (AAC)......Page 178
7.4.3 Cross-coupled oscillator without tail-current generator......Page 180
7.5 Other mechanisms of noise up-conversion......Page 185
7.6 References......Page 190
8.2.1 Binary and ring counters......Page 192
8.2.2 Flip-flop-operated and latch-operated counters......Page 195
8.2.3 Synchronous and asynchronous counters......Page 197
8.3 Programmable dividers......Page 198
8.3.1 Presettable asynchronous dividers......Page 199
8.3.2 Pulse swallowing......Page 200
8.3.3 Series of dual-modulus prescalers......Page 201
8.4.1 Synchronous prescalers......Page 203
8.4.2 Synchronous and asynchronous implementation......Page 204
8.4.3 Phase-switching prescalers......Page 205
8.5.1 CMOS and current-mode logic......Page 208
8.5.2 Static and dynamic latches......Page 209
8.5.3 Practical design issues......Page 213
8.6.1 Link between jitter and phase noise spectrum......Page 214
8.6.2 Jitter of a synchronous counter......Page 215
8.6.3 Flicker noise......Page 217
8.6.4 Noise reduction through synchronization......Page 218
8.7 References......Page 219
9.2 Phase comparison path......Page 221
9.3.1 XOR-based PFD......Page 224
9.3.2 Tri-state PFD......Page 227
9.3.3 Avoidance of dead zone and crossover distortion......Page 229
9.3.4 Offset tri-state PFD......Page 232
9.4.2 Differential input......Page 234
9.4.3 Dynamic effects affecting linearity......Page 236
9.5 Phase-detection noise......Page 239
9.5.1 Charge-pump noise......Page 240
9.5.2 PFD noise......Page 242
9.5.4 Other contributions to in-band noise......Page 243
9.6 References......Page 244
Index......Page 246