Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation: 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers

Front Matter....Pages -
A Power-Aware Online Scheduling Algorithm for Streaming Applications in Embedded MPSoC....Pages 1-10
An Automated Framework for Power-Critical Code Region Detection and Power Peak Optimization of Embedded Software....Pages 11-20
System Level Power Estimation of System-on-Chip Interconnects in Consideration of Transition Activity and Crosstalk....Pages 21-30
Residue Arithmetic for Designing Low-Power Multiply-Add Units....Pages 31-40
An On-Chip Flip-Flop Characterization Circuit....Pages 41-50
A Low-Voltage Log-Domain Integrator Using MOSFET in Weak Inversion....Pages 51-61
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits....Pages 62-72
A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework....Pages 73-83
An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs....Pages 84-93
On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS....Pages 94-104
Self-Timed SRAM for Energy Harvesting Systems....Pages 105-115
L1 Data Cache Power Reduction Using a Forwarding Predictor....Pages 116-125
Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations....Pages 126-136
Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case....Pages 137-149
Hermes-A – An Asynchronous NoC Router with Distributed Routing....Pages 150-159
Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip....Pages 160-169
Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random V T Variations on Timing....Pages 170-179
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis....Pages 180-189
Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations....Pages 190-199
White-Box Current Source Modeling Including Parameter Variation and Its Application in Timing Simulation....Pages 200-210
Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer....Pages 211-217
An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis....Pages 218-227
Clock Network Synthesis with Concurrent Gate Insertion....Pages 228-237
Modeling Time Domain Magnetic Emissions of ICs....Pages 238-249
Power Profiling of Embedded Analog/Mixed-Signal Systems....Pages 250-250
Open-People: Open Power and Energy Optimization PLatform and Estimator....Pages 251-251
Early Power Estimation in Heterogeneous Designs Using SoCLib and SystemC-AMS....Pages 252-252
ASTEC: Asynchronous Technology for Low Power and Secured Embedded Systems....Pages 253-253
OPENTLM and SOCKET: Creating an Open EcoSystem for Virtual Prototyping of Complex SOCs....Pages 254-254
Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs....Pages 255-255
3D Integration for Digital and Imagers Circuits: Opportunities and Challenges....Pages 256-256
Signing Off Industrial Designs on Evolving Technologies....Pages 257-257
Back Matter....Pages -