Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings

Front Matter....Pages -
A Power-Efficient and Scalable Load-Store Queue Design....Pages 1-9
Power Consumption Reduction Using Dynamic Control of Micro Processor Performance....Pages 10-18
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications....Pages 19-29
Dynamic Instruction Cascading on GALS Microprocessors....Pages 30-39
Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width....Pages 40-48
A Retargetable Environment for Power-Aware Code Evaluation: An Approach Based on Coloured Petri Net....Pages 49-58
Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory....Pages 59-68
Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems....Pages 69-78
Optimizing the Configuration of Dynamic Voltage Scaling Points in Real-Time Applications....Pages 79-88
Systematic Preprocessing of Data Dependent Constructs for Embedded Systems....Pages 89-98
Temperature Aware Datapath Scheduling....Pages 99-106
Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform....Pages 107-116
Improving the Memory Bandwidth Utilization Using Loop Transformations....Pages 117-126
Power-Aware Scheduling for Hard Real-Time Embedded Systems Using Voltage-Scaling Enabled Architectures....Pages 127-136
Design of Digital Filters for Low Power Applications Using Integer Quadratic Programming....Pages 137-145
A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction....Pages 146-155
An Energy-Tree Based Routing Algorithm in Wireless Ad-Hoc Network Environments....Pages 156-165
Energy-Aware System-on-Chip for 5 GHz Wireless LANs....Pages 166-176
Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction....Pages 177-186
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits....Pages 187-196
Power Management for Low-Power Battery Operated Portable Systems Using Current-Mode Techniques....Pages 197-206
Power Consumption in Reversible Logic Addressed by a Ramp Voltage....Pages 207-216
Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for V th Assignment and Path Balancing....Pages 217-226
Back Annotation in High Speed Asynchronous Design....Pages 227-236
Optimization of Reliability and Power Consumption in Systems on a Chip....Pages 237-246
Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs....Pages 247-256
A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design....Pages 257-266
Power Supply Selective Mapping for Accurate Timing Analysis....Pages 267-276
Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses....Pages 277-285
PSK Signalling on NoC Buses....Pages 286-296
Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding....Pages 297-307
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing....Pages 308-317
Efficient Simulation of Power/Ground Networks with Package and Vias....Pages 318-328
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation....Pages 329-336
Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates....Pages 337-347
Compact Static Power Model of Complex CMOS Gates....Pages 348-354
Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model....Pages 355-363
Statistical Critical Path Analysis Considering Correlations....Pages 364-373
A CAD Platform for Sensor Interfaces in Low-Power Applications....Pages 374-381
An Integrated Environment for Embedded Hard Real-Time Systems Scheduling with Timing and Energy Constraints....Pages 382-392
Efficient Post-layout Power-Delay Curve Generation....Pages 393-403
Power – Performance Optimization for Custom Digital Circuits....Pages 404-414
Switching-Activity Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs....Pages 415-424
Logic-Level Fast Current Simulation for Digital CMOS Circuits....Pages 425-435
Design of Variable Input Delay Gates for Low Dynamic Power Circuits....Pages 436-445
Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications....Pages 446-455
Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes....Pages 456-465
Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs....Pages 466-476
Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs....Pages 477-487
Static Noise Margin Analysis of Sub-threshold SRAM Cells in Deep Sub-micron Technology....Pages 488-497
An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers....Pages 498-507
Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers....Pages 508-517
Low-Power Aspects of Nonlinear Signal Processing....Pages 518-527
Reducing Energy Consumption of Computer Display by Camera-Based User Monitoring....Pages 528-539
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives....Pages 540-549
A Design Methodology for Secured ICs Using Dynamic Current Mode Logic....Pages 550-560
Power Consumption Characterisation of the Texas Instruments TMS320VC5510 DSP....Pages 561-570
A Method to Design Compact Dual-rail Asynchronous Primitives....Pages 571-580
Enhanced GALS Techniques for Datapath Applications....Pages 581-590
Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study....Pages 591-600
Area-Aware Pipeline Gating for Embedded Processors....Pages 601-608
Fast Low-Power 64-Bit Modular Hybrid Adder....Pages 609-617
Speed Indicators for Circuit Optimization....Pages 618-628
Synthesis of Hybrid CBL/CMOS Cell Using Multiobjective Evolutionary Algorithms....Pages 629-637
Power-Clock Gating in Adiabatic Logic Circuits....Pages 638-646
The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics....Pages 647-656
Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers....Pages 657-665
Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures....Pages 666-673
The Optimal Wire Order for Low Power CMOS....Pages 674-683
Effect of Post-oxidation Annealing on the Electrical Properties of Anodic Oxidized Films in Pure Water....Pages 684-692
Temperature Dependency in UDSM Process....Pages 693-703
Circuit Design Techniques for On-Chip Power Supply Noise Monitoring System....Pages 704-713
A Novel Approach to the Design of a Linearized Widely Tunable Very Low Power and Low Noise Differential Transconductor....Pages 714-723
A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers....Pages 724-732
Digital Hearing Aids: Challenges and Solutions for Ultra Low Power....Pages 733-733
Tutorial Hearing Aid Algorithms....Pages 734-734
Optimization of Digital Audio Processing Algorithms Suitable for Hearing Aids....Pages 735-736
Optimization of Modules for Digital Audio Processing....Pages 737-746
Traveling the Wild Frontier of Ultra Low-Power Design....Pages 747-747
DLV (Deep Low Voltage): Circuits and Devices....Pages 748-748
Wireless Sensor Networks: A New Life Paradigm....Pages 749-749
Cryptography: Circuits and Systems Approach....Pages 750-750
Back Matter....Pages -