Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 13th International Workshop, PATMOS 2003, Turin, Italy, September 10-12, 2003. Proceedings

Front Matter....Pages -
Architectural Challenges for the Next Decade Integrated Platforms....Pages 1-1
Analysis of High-Speed Logic Families....Pages 2-10
Low Voltage, Double-Edge-Triggered Flip Flop....Pages 11-20
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems....Pages 21-30
State Encoding for Low-Power FSMs in FPGA....Pages 31-40
Reduced Leverage of Dual Supply Voltages in Ultra Deep Submicron Technologies....Pages 41-50
A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates....Pages 51-59
CMOS Gate Sizing under Delay Constraint....Pages 60-69
Process Characterisation for Low VTH and Low Power Design....Pages 70-79
Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results....Pages 80-89
Effects of Temperature in Deep-Submicron Global Interconnect Optimization....Pages 90-100
Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits....Pages 101-110
Estimation of Crosstalk Noise for On-Chip Buses....Pages 111-120
A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization....Pages 121-130
Interconnect Driven Low Power High-Level Synthesis....Pages 131-140
Bridging Clock Domains by Synchronizing the Mice in the Mousetrap....Pages 141-150
Power-Consumption Reduction in Asynchronous Circuits Using Delay Path Unequalization....Pages 151-160
New GALS Technique for Datapath Architectures....Pages 161-170
Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders....Pages 171-180
Static Implementation of QDI Asynchronous Primitives....Pages 181-191
The Emergence of Design for Energy Efficiency: An EDA Perspective....Pages 192-192
The Most Complete Mixed-Signal Simulation Solution with ADVance MS....Pages 193-193
Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips....Pages 194-194
Power Management in Synopsys Galaxy Design Platform....Pages 195-195
Open Multimedia Platform for Next-Generation Mobile Devices....Pages 196-196
Statistical Power Estimation of Behavioral Descriptions....Pages 197-207
A Statistical Power Model for Non-synthetic RTL Operators....Pages 208-218
Energy Efficient Register Renaming....Pages 219-228
Stand-by Power Reduction for Storage Circuits....Pages 229-238
A Unified Framework for Power-Aware Design of Embedded Systems....Pages 239-248
A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems....Pages 249-258
High-Level Area and Current Estimation....Pages 259-268
Switching Activity Estimation in Non-linear Architectures....Pages 269-278
Instruction Level Energy Modeling for Pipelined Processors....Pages 279-288
Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level....Pages 289-298
An Adiabatic Charge Pump Based Charge Recycling Design Style....Pages 299-308
Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing....Pages 309-318
Low-Power Response Time Accelerator with Full Resolution for LCD Panel....Pages 319-327
Memory Compaction and Power Optimization for Wavelet-Based Coders....Pages 328-337
Design Space Exploration and Trade-Offs in Analog Amplifier Design....Pages 338-347
Power and Timing Driven Physical Design Automation....Pages 348-357
Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks....Pages 358-368
Remote Power Control of Wireless Network Interfaces....Pages 369-378
Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders....Pages 379-388
A Fully Digital Numerical-Controlled-Oscillator....Pages 389-398
Energy Optimization of High-Performance Circuits....Pages 399-408
Instruction Buffering Exploration for Low Energy Embedded Processors....Pages 409-419
Power-Aware Branch Predictor Update for High-Performance Processors....Pages 420-429
Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms....Pages 430-439
High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder....Pages 440-450
Metric Definition for Circuit Speed Optimization....Pages 451-460
Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI Technologies....Pages 461-470
An Asynchronous Viterbi Decoder for Low-Power Applications....Pages 471-480
Analysis of the Contribution of Interconnect Effects in Energy Dissipation of VLSI Circuits....Pages 481-490
A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application....Pages 491-500
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits....Pages 501-510
A Practical ASIC Methodology for Flexible Clock Tree Synthesis with Routing Blockages....Pages 511-519
Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus....Pages 520-529
Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction....Pages 530-539
A Bottom-Up Approach to On-Chip Signal Integrity....Pages 540-549
Advanced Cell Modeling Techniques Based on Polynomial Expressions....Pages 550-558
RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches....Pages 559-568
Data Dependences Critical Path Evaluation at C/C++ System Level Description....Pages 569-579
A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements....Pages 580-589
Consideration of Control System and Memory Contributions in Practical Resource-Constrained Scheduling for Low Power....Pages 590-598
Low-Power Cache with Successive Tag Comparison Algorithm....Pages 599-606
FPGA Architecture Design and Toolset for Logic Implementation....Pages 607-616
Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis....Pages 617-627
Back Matter....Pages -