Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers

3642118011......Page 1
Integrated Circuit\rand System Design......Page 3
Preface......Page 5
Table of Contents......Page 8
Robust Low Power Embedded SRAM Design: From System to Memory Cell......Page 13
Variability in Advanced Nanometer Technologies: Challenges and Solutions......Page 14
Subthreshold Circuit Design for Ultra-Low-Power Applications......Page 15
SystemC AMS Extensions: New Language – New Methods – New Applications......Page 16
Introduction......Page 17
A Performance Model Using Variant-Timed Petri-Net (VTPN) Model......Page 19
The Proposed Statistical Performance Analysis Method......Page 20
MAX Operation......Page 22
Evaluation and Experimental Results......Page 23
References......Page 25
Introduction......Page 28
Conditional Moments......Page 30
Moment Propagation......Page 31
Gate-to-Gate Delay Correlation......Page 32
Application and Interpretation......Page 34
Validation......Page 35
Conclusions......Page 36
References......Page 37
Introduction......Page 38
Review of RNS Basics......Page 39
Delay Model......Page 40
Sensitivity of Multiply-Add Units to Delay Variation......Page 43
References......Page 46
Random Variability......Page 48
Exponent Monte Carlo......Page 49
Prior Art......Page 50
Analysis Plan......Page 51
Technology Input......Page 52
Vaccination......Page 53
Results......Page 54
References......Page 56
Introduction......Page 58
Inverter Jitter Model......Page 60
Buffer Jitter Model......Page 61
Model Evaluation......Page 62
Asymmetrical Inverters......Page 63
Tunable Delay Repeaters......Page 64
Auto-induced Jitter......Page 65
Conclusion......Page 66
References......Page 67
Introduction......Page 68
An Overview......Page 69
Eye-Gaze Detector......Page 70
Implementation and Evaluation......Page 74
References......Page 77
Introduction......Page 78
Overview of Thermal Analysis Methods......Page 80
SPICE Model and Interconnect Effect......Page 81
Experiment Setup and Results......Page 83
Conclusion and Future Work......Page 86
References......Page 87
Introduction......Page 88
Power Gating Overview......Page 89
Optimum Technique and Experimental Setup......Page 91
Simulation Results......Page 93
References......Page 97
Introduction......Page 98
Related Work......Page 99
Temperature Reduction Methodology Overview......Page 100
Application-Specific Platform Customizations......Page 103
Experimental Results......Page 104
Conclusions......Page 106
References......Page 107
Introduction......Page 108
Clock Gating......Page 110
Data-Driven Clock Gating......Page 111
Combining Enable-Based Clock Gating Conditions......Page 113
Experimental Setup......Page 114
Results on the CIC Filter......Page 115
References......Page 117
Introduction......Page 118
Effect of Signal Gating on Power Supply Noise......Page 119
Effect of Decoupling Capacitance......Page 122
Dynamic Frequency Scaling and Voltage Droop Control......Page 123
Conclusions......Page 126
References......Page 127
Introduction......Page 128
Related Work......Page 129
System Model and Notations......Page 130
Strategy in Detail......Page 131
Experimental Setup, Results and Performance Analysis......Page 135
References......Page 137
Introduction......Page 139
BP-DTMOS Technique......Page 140
BP-DTMOS-DT GDSPOM Procedure......Page 142
Performance......Page 143
References......Page 147
Introduction......Page 148
Static Single-Track Asynchronous Templates......Page 149
Effect of Noise on SSTFB Circuits......Page 150
Creation of a Token Due to Noise on the Channel......Page 151
Creation of a Token Due to Domino Logic Violation......Page 152
Estimation of Noise in Static Single-Track Circuits......Page 153
Maximum Coupling Capacitance......Page 155
Conclusions and Future Work......Page 156
References......Page 157
Introduction......Page 158
EMI in Digital Circuits......Page 159
Modeling EMI in Digital Systems......Page 160
Results......Page 163
References......Page 166
Introduction......Page 168
Power Dissipation Reduction in Clocking Circuits......Page 169
Dual-Edge Triggered State-Retention Scan Flip-Flop......Page 171
Simulation Results......Page 172
Conclusion......Page 175
References......Page 176
Introduction......Page 177
Application Characteristics......Page 179
Simulation Flow......Page 180
Coarse Grain Simulator......Page 181
Cycle Accurate NoC Simulation – Nostrum......Page 182
Simulation Results......Page 183
References......Page 185
Introduction......Page 187
Related Work......Page 189
Dynamic Data Type Optimization......Page 190
Dynamic Data Type Assignment......Page 191
Experimental Results......Page 192
Conclusions......Page 195
References......Page 196
Introduction......Page 198
Related Work......Page 199
Principle of High-Level Power Emulation......Page 200
Power Emulation Unit Architecture......Page 201
Characterization Methodology......Page 202
Power-Aware Software Development Flow......Page 203
Speed Up......Page 204
Power-Aware Application Examples......Page 205
Conclusions......Page 206
References......Page 207
Introduction......Page 208
Invalidation Behavior......Page 209
Invalidation Urgency......Page 210
Applications Behavior Analysis......Page 211
Invalid Read Predictability......Page 213
Invalidation Urgency Predictability......Page 214
Bus Occupancy Reduction......Page 215
References......Page 216
Introduction......Page 218
Overview of the Specifications......Page 219
Possible Hardware/Software Choices......Page 220
Platform Preview......Page 221
Virtual Platform......Page 222
Influence of Parallelism on H264 Performances......Page 223
DBF Function......Page 224
DVFS Capabilities......Page 225
References......Page 226
Introduction......Page 228
Extracting Switching Activity Profiles from SAIF......Page 230
Architecture......Page 231
Switching Analysis Examples......Page 233
Power Optimisation Case Study......Page 235
Concluding Remarks......Page 237
References......Page 238
Introduction......Page 239
Concurrent Clock- and Power-Gating......Page 240
Feasibility Issues......Page 241
CG/PG Flow......Page 242
Mathematical Modeling......Page 243
Introduction to Critical Interconnects......Page 244
Graph Partitioning Heuristics......Page 245
Experimental Set-Up......Page 246
Experimental Data......Page 247
References......Page 248
Introduction......Page 249
Voltage Switching......Page 251
Implementation......Page 252
Energy Saving......Page 254
Experimental Results......Page 256
Conclusions......Page 257
References......Page 258
Introduction......Page 259
On Chip Performance Monitors......Page 260
Efficiency of Voltage Scaling as a Static Process Compensation Technique......Page 261
Discussions and Perspectives......Page 266
References......Page 267
Introduction......Page 268
Latch-Hardening Methods......Page 269
Proposed Soft Error Hardened Latch......Page 271
Simulation Result......Page 272
References......Page 276
Introduction......Page 278
Monitoring System Proposal......Page 279
Integration Flow......Page 281
Critical Paths Choice......Page 282
Specific Clock Tree Cell Insertion......Page 283
Results......Page 284
References......Page 287
Introduction......Page 288
Methodological Aspects......Page 289
Flow Chart of the Computing Device......Page 291
Practical Implementation of the Computing Device......Page 293
References......Page 296
Introduction......Page 298
Concept of Design Approach......Page 299
Multi-access Arbiters......Page 300
N×M Arbiter Architecture......Page 301
Tile-Based Arbiter Solution......Page 302
Simulation Results......Page 306
Conclusions and Future Work......Page 307
References......Page 308
Introduction......Page 309
Proposed Methodology......Page 310
Modeling of Complex Gate AOI21......Page 311
Simulation Experiments and Analysis of Results......Page 315
References......Page 318
Introduction......Page 319
Free Power Recovery......Page 321
FPR vs. FAR......Page 324
Implementation Flow......Page 326
Conclusion......Page 327
References......Page 328
Introduction......Page 329
Loading Effect......Page 330
Routing Resistance Influence......Page 331
Loading Effect in Different Technology Process......Page 332
Routing Resistance Influence......Page 333
References......Page 336
Introduction......Page 338
Advanced Encryption Standard (AES)......Page 339
Application Specific Processor for WSN......Page 340
AES Code Optimization......Page 341
Optimization of Critical Kernels......Page 342
Storing Partial Results......Page 343
XTIMEx4 Functional Unit......Page 344
Results......Page 345
Conclusions and Future Work......Page 346
References......Page 347
Introduction......Page 348
Design Specification......Page 349
Circuit Design......Page 351
Measurement Result......Page 355
References......Page 357
Introduction......Page 359
Implementation of the R-Wave Detector......Page 360
Architectural Folding......Page 362
Detector Performance......Page 363
Sub-VT Energy Model......Page 364
Sub-VT Operation Mode......Page 365
References......Page 368
Introduction......Page 369
Dynamic Domino Logic and D3L......Page 370
Domino and D3L High-Speed Adder Designs......Page 371
Optimized Kogge-Stone Carry Propagation Tree......Page 373
Split-Path Gate Level Implementation of the Dot Operators......Page 375
32-Bit Kogge-Stone Implementation and Comparison Results......Page 376
Conclusion......Page 377
References......Page 378
Author Index......Page 379