Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings

Front Matter....Pages -
Design of Parallel Implementations by Means of Abstract Dynamic Critical Path Based Profiling of Complex Sequential Algorithms....Pages 1-11
Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism....Pages 12-23
Handheld System Energy Reduction by OS-Driven Refresh....Pages 24-35
Delay Constrained Register Transfer Level Dynamic Power Estimation....Pages 36-46
Circuit Design Style for Energy Efficiency: LSDL and Compound Domino....Pages 47-55
Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage....Pages 56-65
Leakage Power Characterization Considering Process Variations....Pages 66-74
Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance....Pages 75-83
System Level Multi-bank Main Memory Configuration for Energy Reduction....Pages 84-94
SRAM CP: A Charge Recycling Design Schema for SRAM....Pages 95-106
Compiler-Driven Leakage Energy Reduction in Banked Register Files....Pages 107-116
Impact of Array Data Flow Analysis on the Design of Energy-Efficient Circuits....Pages 117-126
Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations....Pages 127-136
Low-Power Adaptive Bias Amplifier for a Large Supply-Range Linear Voltage Regulator....Pages 137-147
Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design....Pages 148-156
Power Modeling of a NoC Based Design for High Speed Telecommunication Systems....Pages 157-168
Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance....Pages 169-180
Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology....Pages 181-190
Two Efficient Synchronous $\\Leftrightarrow$ Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures....Pages 191-202
Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters....Pages 203-213
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective....Pages 214-224
A Clock Generator Driven by a Unified-CBiCMOS Buffer Driver for High Speed and Low Energy Operation....Pages 225-236
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique....Pages 237-246
Low Power Distance Measurement Unit for Real-Time Hardware Motion Estimators....Pages 247-255
Reducing Energy Dissipation of Wireless Sensor Processors Using Silent-Store-Filtering MoteCache....Pages 256-266
A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus....Pages 267-279
Methodology for Dynamic Power Verification of Contactless Smartcards....Pages 280-291
New Battery Status Checking Method for Implantable Biomedical Applications....Pages 292-300
Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis....Pages 301-310
A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique....Pages 311-318
Zephyr: A Static Timing Analyzer Integrated in a Trans-hierarchical Refinement Design Flow....Pages 319-328
Receiver Modeling for Static Functional Crosstalk Analysis....Pages 329-339
Modeling of Crosstalk Fault in Defective Interconnects....Pages 340-349
Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits....Pages 350-359
Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations....Pages 360-369
IR-drop Reduction Through Combinational Circuit Partitioning....Pages 370-381
Low-Power Register File Based on Adiabatic Logic Circuits....Pages 382-392
High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI....Pages 393-402
Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources....Pages 403-414
An FPGA Power Aware Design Flow....Pages 415-424
The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing....Pages 425-438
Optimization of Master-Slave Flip-Flops for High-Performance Applications....Pages 439-449
Hierarchical Modeling of a Fractional Phase Locked Loop....Pages 450-457
Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs....Pages 458-467
Statistical Characterization of Library Timing Performance....Pages 468-476
Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors....Pages 477-485
Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS....Pages 486-495
Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations....Pages 496-503
Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling....Pages 504-513
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors....Pages 514-523
Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications....Pages 524-531
Spectral Analysis of the On-Chip Waveforms to Generate Guidelines for EMC-Aware Design....Pages 532-542
A Scalable Power Modeling Approach for Embedded Memory Using LIB Format....Pages 543-552
Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors....Pages 553-562
A CMOS Compatible Charge Recovery Logic Family for Low Supply Voltages....Pages 563-572
A Framework for Estimating Peak Power in Gate-Level Circuits....Pages 573-582
QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis....Pages 583-592
Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm....Pages 593-602
Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry....Pages 603-613
A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits....Pages 614-623
Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis....Pages 624-633
Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks....Pages 634-644
A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits....Pages 645-657
Nanoelectronics: Challenges and Opportunities....Pages 658-658
Static and Dynamic Power Reduction by Architecture Selection....Pages 659-668
Asynchronous Design for High-Speed and Low-Power Circuits....Pages 669-669
Design for Volume Manufacturing in the Deep Submicron ERA....Pages 670-670
The Holy Grail of Holistic Low-Power Design....Pages 671-671
Top Verification of Low Power System with “Checkerboard” Approach....Pages 672-672
The Power Forward Initiative....Pages 673-673
Back Matter....Pages -