Implementation of digital-serial filters

Processing Elements 39......Page 7
Case Study 135......Page 8
References 175......Page 9
Introduction......Page 11
1.1 Low Power Design in CMOS......Page 12
1.1.1.1 Minimum Energy-Delay Product......Page 13
1.1.1.3 Minimizing Effective Switching Capacitance......Page 14
1.1.1.4 Design Methodology for Low Power......Page 15
1.2 Digital Filters......Page 16
1.2.1 FIR Filter......Page 17
1.2.2 IIR Filter......Page 19
1.2.2.1 Bireciprocal LWDF......Page 22
1.3 Outline......Page 23
1.4.1 List of Publications......Page 24
Implementation of DSP Algorithms......Page 29
2.1 Timing of Operations......Page 30
2.2 Pipelining and Interleaving......Page 31
2.2.1 Interleaving......Page 32
2.2.2 Latency Models......Page 33
2.2.4 Latch Level Pipelining......Page 35
2.3 Maximal Sample Frequency......Page 37
2.4 Algorithm Transformations......Page 38
2.5 Implementation of DSP Algorithms......Page 39
2.5.1 Precedence Graph......Page 40
2.5.2 Computation Graph......Page 41
2.5.3 Operation Scheduling......Page 42
2.5.4 Unfolding and Cyclic Scheduling of Recursive Algorithms......Page 43
2.5.5 Unfolding and Cyclic Scheduling of Non-Recursive Algorithms......Page 44
2.5.6 Mapping to Hardware......Page 45
3.1 Number Representation......Page 49
3.1.2 Signed Digit......Page 50
3.2 Bit-Serial Arithmetic......Page 51
3.2.1 Bit-Serial Adder......Page 52
3.2.2 Bit-Serial Subtractor......Page 53
3.2.3 Bit-Serial Multiplier......Page 54
3.3.1 Digit-Serial Adder......Page 56
3.3.1.1 Digit-Serial Ripple-Carry Adders......Page 59
3.3.1.2 Digit-Serial Carry-Look-Ahead Adders......Page 60
3.3.1.3 Implementation of Digit-Serial Adders......Page 63
3.3.1.4 Result for Adders with Latency Model 1......Page 64
Example 1:......Page 67
3.3.1.5 Result for Adders with Latency Model 0......Page 69
3.3.2.1 Unfolding of Bit-Serial Multiplier......Page 72
3.3.2.2 Fixed Coefficient Digit-Serial Multipliers......Page 74
3.3.2.3 Logic Realization for the Digit-Serial Multiplier......Page 76
3.3.2.4 Results for the Digit-Serial Multiplier......Page 77
3.4.1 Conclusions for Implementation of Digit-Serial Adders......Page 80
3.4.2 Conclusions for Implementation of Digit-Serial Multipliers......Page 81
4.1.1 Circuit Techniques for Low Power......Page 83
4.1.2 A Small Logic Style Survey......Page 85
4.2.1 Non-Overlapping Pseudo Two-Phase Clocking Scheme......Page 88
4.2.2 The C2MOS-Latches......Page 89
4.2.3.1 Exclusive OR......Page 90
4.2.3.3 Full Adder......Page 91
4.3.1.1 Precharged Latches......Page 92
4.3.1.2 Non-Precharged Latches......Page 93
4.3.2.1 Exclusive OR......Page 94
4.3.2.2 Multiplexer......Page 95
4.4.1 The STC-Latches......Page 96
4.4.2 Realization of DCVS-Logic Gates......Page 97
4.4.2.1 Exclusive OR......Page 99
4.4.3 Layout of DCVS Gates......Page 100
4.5.1 The N-Latch in the DN-Logic Style......Page 101
4.5.2 The P-Latches in the DN-Logic Style......Page 102
4.5.2.1 The Full P-latch II......Page 105
4.5.2.3 Unbalanced Logic Depths......Page 106
4.5.3 The D Flip-Flops in the DN-Logic Style......Page 107
4.5.4 The Use of the Latches and Flip-Flops......Page 108
4.5.4.3 Utilizing the Non-Latched Output in the P-Latch......Page 109
4.5.5 Realization of Logic Gates in the DN-Logic Style......Page 110
4.6 Evaluation of the DN-Logic Style......Page 112
4.6.1.1 Bit-Serial Adder Realized with Latches......Page 113
4.6.1.3 Comparison of Performance......Page 115
4.6.2 P-Latch I versus P-Latch II......Page 116
4.6.3.1 DC Analysis of a DCVS Gate......Page 119
Operating mode analysis......Page 121
4.6.3.3 Circuit Threshold Voltage Calculation......Page 122
4.6.3.5 Clock Slope Sensitivity......Page 123
4.6.3.6 Voltage Scaling Sensitivity......Page 124
4.7 Comparison of the Logic Styles......Page 125
4.7.1 Key Numbers of the Logic Styles......Page 126
4.7.1.1 Transistor Count......Page 127
4.7.1.2 Clock Load......Page 128
4.7.1.3 Number of Stacked Transistors......Page 129
4.7.1.4 Number of Switching Nodes......Page 130
4.7.2 Comparison Based on a Complex Multiplier......Page 131
4.7.2.1 The Complex Multiplier Based on Distributed Arithmetic......Page 132
4.7.2.2 Transistor Density for the Complex Multiplier......Page 136
4.7.2.4 Chip Area for the Complex Multiplier......Page 137
4.7.2.6 Throughput for the Complex Multiplier......Page 138
4.7.2.7 Power Consumption for the Complex Multiplier......Page 139
4.7.2.9 Hardware Duplication for Constant Throughput......Page 140
4.7.2.10 Voltage Scaling for Constant Throughput......Page 141
Example......Page 142
4.8 Choice of Logic Style......Page 143
5.1 Filter Specification......Page 145
5.2.1 FIR Filter......Page 146
5.2.3 Filter Attenuations......Page 148
5.3.1.1 Algorithm Transformations of the FIR Filter......Page 149
5.3.1.2 Precedence Graphs for the FIR Filter......Page 150
5.3.1.3 Computation Graphs for the FIR Filter......Page 151
5.3.1.4 Unfolding of the FIR Filter......Page 152
5.3.1.5 Hardware Structure for the FIR Filter......Page 155
5.3.2.1 Algorithm Transformations of the IIR Filter......Page 156
5.3.2.2 Precedence Graph for the IIR filter......Page 157
5.3.2.4 Unfolding of the IIR Filter......Page 158
5.3.2.5 Hardware Structure for the IIR Filter......Page 159
5.4.2 The Multipliers......Page 160
5.4.2.1 The Multipliers in the FIR Filter......Page 161
5.4.2.2 The Multiplier in the IIR Filter......Page 163
5.4.3 Circuit Implementation......Page 164
5.5.1 Throughput Analysis for the FIR Filter......Page 165
5.5.2 Energy Analysis for the FIR Filter......Page 169
5.5.3 Constant Throughput for the FIR Filter......Page 173
5.5.4 Throughput Analysis for the IIR Filter......Page 174
5.5.4.1 Latency Model 0......Page 175
5.5.4.2 Latency Model 1......Page 176
5.5.4.3 Fractional Latency Model......Page 177
5.5.5 Energy Analysis for the IIR Filter......Page 178
5.6.1 Conclusion of the FIR Filter Implementation......Page 179
5.6.2 Conclusion of the IIR Filter Implementation......Page 180
6.1 Algorithm Level......Page 181
6.2.1 Digit-Serial Adders......Page 182
6.3 Circuit Level......Page 183
References......Page 185